Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
235
Rev 01.24
Table 8-8. Clock Prescaler Values
Prescale Value
Total Divisor
Value
Maximum
Bus Clock
(1)
1. Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is
shown in this column.
Minimum
Bus Clock
(2)
2. Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency
is shown in this column.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Divide by 2
Divide by 4
Divide by 6
Divide by 8
Divide by 10
Divide by 12
Divide by 14
Divide by 16
Divide by 18
Divide by 20
Divide by 22
Divide by 24
Divide by 26
Divide by 28
Divide by 30
Divide by 32
Divide by 34
Divide by 36
Divide by 38
Divide by 40
Divide by 42
Divide by 44
Divide by 46
Divide by 48
Divide by 50
Divide by 52
Divide by 54
Divide by 56
Divide by 58
Divide by 60
Divide by 62
Divide by 64
4 MHz
8 MHz
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
36 MHz
40 MHz
44 MHz
48 MHz
52 MHz
56 MHz
60 MHz
64 MHz
68 MHz
72 MHz
76 MHz
80 MHz
84 MHz
88 MHz
92 MHz
96 MHz
100 MHz
104 MHz
108 MHz
112 MHz
116 MHz
120 MHz
124 MHz
128 MHz
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
9 MHz
10 MHz
11 MHz
12 MHz
13 MHz
14 MHz
15 MHz
16 MHz
17 MHz
18 MHz
19 MHz
20 MHz
21 MHz
22 MHz
23 MHz
24 MHz
25 MHz
26 MHz
27 MHz
28 MHz
29 MHz
30 MHz
31 MHz
32 MHz
Summary of Contents for MC9S12C Family
Page 689: ......
