Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
253
Rev 01.24
Figure 9-1. CRG Block Diagram
9.2
External Signal Description
This section lists and describes the signals that connect off chip.
9.2.1
V
DDPLL
, V
SSPLL
— PLL Operating Voltage, PLL Ground
These pins provides operating voltage (V
DDPLL
) and ground (V
SSPLL
) for the PLL circuitry. This allows
the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required V
DDPLL
and V
SSPLL
must be connected properly.
9.2.2
XFC — PLL Loop Filter Pin
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter
to eliminate the VCO input ripple. The value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. Refer to the device overview chapter
for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be
tied to V
DDPLL
.
CRG
Registers
Clock and Reset
COP
RESET
RTI
PLL
XFC
V
DDPLL
V
SSPLL
Oscil-
EXTAL
XTAL
Control
Bus Clock
System Reset
Oscillator Clock
PLLCLK
OSCCLK
Core Clock
Clock
Monitor
CM fail
Clock Quality
Checker
Reset
Generator
XCLKS
Power-on Reset
Low Voltage Reset
1
COP Timeout
Real-Time Interrupt
PLL Lock Interrupt
Self-Clock Mode
Interrupt
lator
Voltage
Regulator
1
Refer to the device overview section for availability of the low-voltage reset feature.
Summary of Contents for MC9S12C Family
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