Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
269
Rev 01.24
9.4.2
System Clocks Generator
Figure 9-17. System Clocks Generator
The clock generator creates the clocks used in the MCU (see
). The gating condition placed on
top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting
of the respective configuration bits.
The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The
memory blocks use the bus clock. If the MCU enters self-clock mode (see
”), oscillator clock source is switched to PLLCLK running at its minimum frequency f
SCM
. The bus
clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU.
The core clock is twice the bus clock as shown in
. But note that a CPU cycle corresponds to
one bus clock.
PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned
off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum
OSCILLATOR
PHASE
LOCK
LOOP
EXTAL
XTAL
SYSCLK
RTI
OSCCLK
PLLCLK
CLOCK PHASE
GENERATOR
Bus Clock
Clock
Monitor
1
0
PLLSEL or SCM
÷
2
Core Clock
COP
Oscillator
Oscillator
= Clock Gate
Gating
Condition
WAIT(CWAI,SYSWAI),
STOP
WAIT(RTIWAI),
STOP(PSTP,PRE),
RTI enable
WAIT(COPWAI),
STOP(PSTP,PCE),
COP enable
WAIT(SYSWAI),
STOP
STOP(PSTP)
1
0
SCM
WAIT(SYSWAI),
STOP
Clock
Clock
(running during
Pseudo-Stop Mode
Summary of Contents for MC9S12C Family
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