Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
349
Rev 01.24
12.2.4
PWM2 — Pulse Width Modulator Channel 2 Pin
This pin serves as waveform output of PWM channel 2.
12.2.5
PWM1 — Pulse Width Modulator Channel 1 Pin
This pin serves as waveform output of PWM channel 1.
12.2.6
PWM0 — Pulse Width Modulator Channel 0 Pin
This pin serves as waveform output of PWM channel 0.
12.3
Memory Map and Register Definition
This subsection describes in detail all the registers and register bits in the PWM8B6CV1 module.
The special-purpose registers and register bit functions that would not normally be made available to
device end users, such as factory test control registers and reserved registers are clearly identified by means
of shading the appropriate portions of address maps and register diagrams. Notes explaining the reasons
for restricting access to the registers and functions are also explained in the individual register descriptions.
12.3.1
Module Memory Map
The following paragraphs describe the content of the registers in the PWM8B6CV1 module. The base
address of the PWM8B6CV1 module is determined at the MCU level when the MCU is defined. The
register decode map is fixed and begins at the first address of the module address offset.
shows
the registers associated with the PWM and their relative offset from the base address. The register detail
description follows the order in which they appear in the register map.
Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented
functions are indicated by shading the bit.
shows the memory map for the PWM8B6CV1 module.
NOTE
Register address = base a address offset, where the base address is
defined at the MCU level and the address offset is defined at the module
level.
Summary of Contents for MC9S12C Family
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