Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
367
Rev 01.24
Read: anytime
Write: anytime
12.3.2.14 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:
•
The effective period ends
•
The counter is written (counter resets to 0x0000)
•
The channel is disabled
In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,
not some variation in between. If the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
Module Base + 0x0015
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 12-24. PWM Channel Period Registers (PWMPER3)
Module Base + 0x0016
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 12-25. PWM Channel Period Registers (PWMPER4)
Module Base + 0x0017
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 12-26. PWM Channel Period Registers (PWMPER5)
Summary of Contents for MC9S12C Family
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