Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
368
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24
NOTE
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
Reference
Section 12.4.2.3, “PWM Period and Duty
”
for more information.
NOTE
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is 1, the output starts
high and then goes low when the duty count is reached, so the duty registers
contain a count of the high time. If the polarity bit is 0, the output starts low
and then goes high when the duty count is reached, so the duty registers
contain a count of the low time.
To calculate the output duty cycle (high time as a % of period) for a particular channel:
•
Polarity = 0 (PPOLx = 0)
Duty cycle = [(PWMPERx PWMDTYx)/PWMPERx] * 100%
•
Polarity = 1 (PPOLx = 1)
Duty cycle = [PWMDTYx / PWMPERx] * 100%
•
For boundary case programming values, please refer to
Section 12.4.2.8, “PWM Boundary Cases.”
Module Base + 0x0018
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
1
1
1
1
1
1
1
1
Figure 12-27. PWM Channel Duty Registers (PWMDTY0)
Module Base + 0x0019
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
1
1
1
1
1
1
1
1
Figure 12-28. PWM Channel Duty Registers (PWMDTY1)
Module Base + 0x001A
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
1
1
1
1
1
1
1
1
Figure 12-29. PWM Channel Duty Registers (PWMDTY2)
Summary of Contents for MC9S12C Family
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