manualshive.com logo in svg

Freescale Semiconductor MC9S12C Family, Reference Manual

The Freescale Semiconductor MC9S12C Family is a cutting-edge product in the semiconductor industry. Unlock its full potential with the comprehensive "Reference Manual" available for free download on our website. Access all the essential information and instructions needed and embrace the power of this remarkable product.

Share
Download
background image

Chapter 14 Serial Peripheral Interface (SPIV3) Block Description

428

MC9S12C-Family / MC9S12GC-Family

Freescale Semiconductor

Rev 01.24

In master mode, with slave select output enabled the SS line is always deasserted and reasserted between
successive transfers for at least minimum idle time.

14.4.3.3

CPHA = 1 Transfer Format

Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin,
the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the
CPHA bit at the beginning of the 8-cycle transfer operation.

The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first
edge commands the slave to transfer its first data bit to the serial data input pin of the master.

A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the
master and slave.

When the third edge occurs, the value previously latched from the serial data input pin is shifted into the
LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master
data is coupled out of the serial data output pin of the master to the serial input pin on the slave.

This process continues for a total of 16 edges on the SCK line with data being latched on even numbered
edges and shifting taking place on odd numbered edges.

Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and
is transferred to the parallel SPI Data Register after the last bit is shifted in.

After the 16th SCK edge:

•

Data that was previously in the SPI Data Register of the master is now in the data register of the
slave, and data that was in the data register of the slave is in the master.

•

The SPIF flag bit in SPISR is set indicating that the transfer is complete.

Figure 14-10

shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or

slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master
and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the
master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or
reconfigured as a general-purpose output not affecting the SPI.

The SS line can remain active low between successive transfers (can be tied low at all times). This format
is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data
line.

•

Back-to-back transfers in master mode

In master mode, if a transmission has completed and a new data byte is available in the SPI Data Register,
this byte is send out immediately without a trailing and minimum idle time.

The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one
half SCK cycle after the last SCK edge.

Summary of Contents for MC9S12C Family

Page 1: ...HCS12 Microcontrollers freescale com MC9S12C Family MC9S12GC Family Reference Manual MC9S12C128 Rev 01 24 05 2010 ...

Page 2: ...d 16MHz option for 128K 96K and 64K versions Minor corrections following review Oct 2005 01 16 Added outstanding flash module descriptions Added EPP package options Corrected and Enhanced recommended PCB layouts Dec 2005 01 17 Added note to PIM block diagram figure Dec 2005 01 18 Added PIM rerouting information to 80 pin package diagram Jan 2006 01 19 Modified LVI levels in electrical parameter se...

Page 3: ...r Area Network S12MSCANV2 287 Chapter 11 Oscillator OSCV2 343 Chapter 12 Pulse Width Modulator PWM8B6CV1 347 Chapter 13 Serial Communications Interface S12SCIV2 383 Chapter 14 Serial Peripheral Interface SPIV3 413 Chapter 15 Timer Module TIM16B8CV1 435 Chapter 16 Dual Output Voltage Regulator VREG3V3V2 463 Chapter 17 16 Kbyte Flash Module S12FTS16KV1 471 Chapter 18 32 Kbyte Flash Module S12FTS32KV...

Page 4: ...4 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 Appendix E Ordering Information 686 ...

Page 5: ...Pins 55 1 4 System Clock Description 57 1 5 Modes of Operation 57 1 5 1 Chip Configuration Summary 57 1 5 2 Security 58 1 5 3 Low Power Modes 59 1 6 Resets and Interrupts 60 1 6 1 Vectors 60 1 6 2 Resets 62 1 7 Device Specific Information and Module Dependencies 62 1 7 1 PPAGE 62 1 7 2 BDM Alternate Clock 63 1 7 3 Extended Address Range Emulation Implications 63 1 7 4 VREGEN 64 1 7 5 VDD1 VDD2 VSS...

Page 6: ...n 108 Chapter 3 Module Mapping Control MMCV4 Block Description 3 1 Introduction 109 3 1 1 Features 110 3 1 2 Modes of Operation 110 3 2 External Signal Description 110 3 3 Memory Map and Register Definition 110 3 3 1 Module Memory Map 110 3 3 2 Register Descriptions 112 3 4 Functional Description 122 3 4 1 Bus Control 122 3 4 2 Address Decoding 122 3 4 3 Memory Expansion 124 Chapter 4 Multiplexed ...

Page 7: ...oder 163 5 7 Exception Priority 163 Chapter 6 Background Debug Module BDMV4 Block Description 6 1 Introduction 165 6 1 1 Features 165 6 1 2 Modes of Operation 166 6 2 External Signal Description 167 6 2 1 BKGD Background Interface Pin 167 6 2 2 TAGHI High Byte Instruction Tagging Pin 167 6 2 3 TAGLO Low Byte Instruction Tagging Pin 167 6 3 Memory Map and Register Definition 168 6 3 1 Module Memory...

Page 8: ...ry Map 196 7 3 2 Register Descriptions 196 7 4 Functional Description 212 7 4 1 DBG Operating in BKP Mode 212 7 4 2 DBG Operating in DBG Mode 214 7 4 3 Breakpoints 221 7 5 Resets 222 7 6 Interrupts 222 Chapter 8 Analog to Digital Converter ATD10B8C Block Description 8 1 Introduction 223 8 1 1 Features 223 8 1 2 Modes of Operation 223 8 1 3 Block Diagram 224 8 2 Signal Description 225 8 2 1 AN7 ETR...

Page 9: ...r Pin 253 9 2 3 RESET Reset Pin 254 9 3 Memory Map and Register Definition 254 9 3 1 Module Memory Map 254 9 3 2 Register Descriptions 255 9 4 Functional Description 266 9 4 1 Phase Locked Loop PLL 266 9 4 2 System Clocks Generator 269 9 4 3 Clock Monitor CM 270 9 4 4 Clock Quality Checker 270 9 4 5 Computer Operating Properly Watchdog COP 272 9 4 6 Real Time Interrupt RTI 272 9 4 7 Modes of Opera...

Page 10: ...age 324 10 4 3 Identifier Acceptance Filter 327 10 4 4 Modes of Operation 333 10 4 5 Low Power Options 334 10 4 6 Reset Initialization 339 10 4 7 Interrupts 339 10 5 Initialization Application Information 341 10 5 1 MSCAN initialization 341 Chapter 11 Oscillator OSCV2 Block Description 11 1 Introduction 343 11 1 1 Features 343 11 1 2 Modes of Operation 343 11 2 External Signal Description 344 11 2...

Page 11: ...Description 371 12 4 1 PWM Clock Select 371 12 4 2 PWM Channel Timers 374 12 5 Resets 381 12 6 Interrupts 381 Chapter 13 Serial Communications Interface S12SCIV2 Block Description 13 1 Introduction 383 13 1 1 Glossary 383 13 1 2 Features 383 13 1 3 Modes of Operation 384 13 1 4 Block Diagram 385 13 2 External Signal Description 385 13 2 1 TXD SCI Transmit Pin 385 13 2 2 RXD SCI Receive Pin 385 13 ...

Page 12: ... 5 Special Features 430 14 4 6 Error Conditions 431 14 4 7 Operation in Run Mode 432 14 4 8 Operation in Wait Mode 432 14 4 9 Operation in Stop Mode 432 14 5 Reset 433 14 6 Interrupts 433 14 6 1 MODF 433 14 6 2 SPIF 433 14 6 3 SPTEF 433 Chapter 15 Timer Module TIM16B8CV1 Block Description 15 1 Introduction 435 15 1 1 Features 435 15 1 2 Modes of Operation 436 15 1 3 Block Diagrams 436 15 2 Externa...

Page 13: ...2 Chapter 16 Dual Output Voltage Regulator VREG3V3V2 Block Description 16 1 Introduction 463 16 1 1 Features 463 16 1 2 Modes of Operation 463 16 1 3 Block Diagram 464 16 2 External Signal Description 465 16 2 1 VDDR Regulator Power Input 465 16 2 2 VDDA VSSA Regulator Reference Supply 465 16 2 3 VDD VSS Regulator Output1 Core Logic 466 16 2 4 VDDPLL VSSPLL Regulator Output2 PLL 466 16 2 5 VREGEN ...

Page 14: ... 2 Operating Modes 500 17 4 3 Flash Module Security 500 17 4 4 Flash Reset Sequence 502 17 4 5 Interrupts 502 Chapter 18 32 Kbyte Flash Module S12FTS32KV1 18 1 Introduction 503 18 1 1 Glossary 503 18 1 2 Features 503 18 1 3 Modes of Operation 504 18 1 4 Block Diagram 504 18 2 External Signal Description 504 18 3 Memory Map and Registers 505 18 3 1 Module Memory Map 505 18 3 2 Register Descriptions...

Page 15: ...s 575 20 1 3 Modes of Operation 576 20 1 4 Block Diagram 576 20 2 External Signal Description 577 20 3 Memory Map and Registers 577 20 3 1 Module Memory Map 577 20 3 2 Register Descriptions 583 20 4 Functional Description 595 20 4 1 Flash Command Operations 595 20 4 2 Operating Modes 609 20 4 3 Flash Module Security 609 20 4 4 Flash Reset Sequence 611 20 4 5 Interrupts 611 Chapter 21 128 Kbyte Fla...

Page 16: ...terrupts 646 Appendix A Electrical Characteristics A 1 General 647 A 2 ATD Characteristics 658 A 3 MSCAN 663 A 4 Reset Oscillator and PLL 663 A 5 NVM Flash and EEPROM 669 A 6 SPI 673 A 7 Voltage Regulator 677 Appendix B Emulation Information B 1 General 679 Appendix C Package Information C 1 General 681 Appendix D Derivative Differences Appendix E Ordering Information ...

Page 17: ...patible module MSCAN12 All MC9S12C Family MC9S12GC Family devices feature full 16 bit data paths throughout The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements In addition to the I O ports available in each module up to 10 dedicated I O port bits are available with wake up capability from stop or wait mode The devices are availabl...

Page 18: ... self test operation Timer module TIM 8 channel timer Each channel configurable as either input capture or output compare Simple PWM mode Modulo reset of timer counter 16 bit pulse accumulator External event counting Gated time accumulation PWM module Programmable period and duty cycle 8 bit 6 channel or 16 bit 3 channel Separate control for each pulse width and duty cycle Center aligned or left a...

Page 19: ...FP or 80 pin QFP package Up to 58 I O lines with 5V input and drive capability 80 pin package Up to 2 dedicated 5V input only lines IRQ XIRQ 5V 8 A D converter inputs and 5V I O Development support Single wire background debug mode BDM On chip hardware breakpoints Enhanced DBG12 debug features 1 1 2 Modes of Operation User modes expanded modes are only available in the 80 pin package version Norma...

Page 20: ...DDPLL Multiplexed Address Data Bus Multiplexed Wide Bus IRQ LSTRB TAGLO ECLK MODA IPIPE0 PA4 PA3 PA2 PA1 PA0 PA7 PA6 PA5 TEST VPP ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR15 ADDR14 ADDR13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA15 DATA14 DATA13 PB4 PB3 PB2 PB1 PB0 PB7 PB6 PB5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 ADDR7 ADDR6 ADDR5 DATA4 DATA3 DATA2 DATA1 DATA0 DATA7 DATA6 DATA5 PE3 PE4 PE5 PE6 PE7 PE0 PE1 PE2 DD...

Page 21: ...2F Core DBG 16 0x0030 0x0033 Core PPAGE 1 1 External memory paging is not supported on this device Section 1 7 1 PPAGE 4 0x0034 0x003F Clock and reset generator CRG 12 0x0040 0x006F Standard timer module TIM 48 0x0070 0x007F Reserved 16 0x0080 0x009F Analog to digital converter ATD 32 0x00A0 0x00C7 Reserved 40 0x00C8 0x00CF Serial communications interface SCI 8 0x00D0 0x00D7 Reserved 8 0x00D8 0x00...

Page 22: ...e 0xC000 0xFFFF 16K Fixed Flash EEPROM 0x8000 0xBFFF 16K Page Window 8 16K Flash EEPROM Pages 0x4000 0x7FFF 16K Fixed Flash EEPROM 0x3000 0x3FFF 0x0000 0x03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 4K Boundary 4K Bytes RAM 0x3000 The figure shows a useful map which is not the map out of reset After reset the map is 0x0000 0x03FF Register Space 0x0000 0x0FFF 4K RAM only 3K vi...

Page 23: ... 0xC000 0xFFFF 16K Fixed Flash EEPROM 0x8000 0xBFFF 16K Page Window 6 16K Flash EEPROM Pages 0x4000 0x7FFF 16K Fixed Flash EEPROM 0x3000 0x3FFF 0x0000 0x03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 4K Boundary 4K Bytes RAM 0x3000 The figure shows a useful map which is not the map out of reset After reset the map is 0x0000 0x03FF Register Space 0x0000 0x0FFF 4K RAM only 3K vis...

Page 24: ... 0xC000 0xFFFF 16K Fixed Flash EEPROM 0x8000 0xBFFF 16K Page Window 4 16K Flash EEPROM Pages 0x4000 0x7FFF 16K Fixed Flash EEPROM 0x3000 0x3FFF 0x0000 0x03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 4K Boundary 4K Bytes RAM 0x3000 The figure shows a useful map which is not the map out of reset After reset the map is 0x0000 0x03FF Register space 0x0000 0x0FFF 4K RAM only 3K vis...

Page 25: ...16K Fixed Flash EEPROM 0x8000 0xBFFF 16K Page Window 2 16K Flash EEPROM Pages 0x3800 0x3FFF 0x0000 0x03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 2K Boundary 2K Bytes RAM 0x3800 The figure shows a useful map which is not the map out of reset After reset the map is 0x0000 0x03FF Register space 0x0800 0x0FFF 2K RAM VECTORS Flash erase sector size is 512 bytes PAGE MAP 0x003E 0x...

Page 26: ...DM If Active 0xC000 0xFFFF 16K Fixed Flash EEPROM 0x3C00 0x3FFF 0x0000 0x03FF 1K Register Space Mappable to any 2K Boundary Mappable to any 2K Boundary 1K Bytes RAM 0x3C00 The figure shows a useful map which is not the map out of reset After reset the map is 0x0000 0x03FF Register Space 0x0C00 0x0FFF 1K RAM VECTORS The 16K flash array page 0x003F is also visible in the PPAGE window when PPAGE regi...

Page 27: ... DDRA Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0x0003 DDRB Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0x0004 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0005 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0006 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0007 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0008 PORTE Read Bit 7 6 5 4 3 2 Bit 1 Bit 0 Write 0x0009 DDRE Read Bit 7 6 5 4 3 Bit 2 0 0 Write 0x000A PEAR Read NOACCE 0 PIPOE NECLK LST...

Page 28: ... 0 0 0 0 Write 0x0015 0x0016 INT Map 1 of 2 HCS12 Interrupt Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0015 ITCR Read 0 0 0 WRINT ADR3 ADR2 ADR1 ADR0 Write 0x0016 ITEST Read INTE INTC INTA INT8 INT6 INT4 INT2 INT0 Write 0x0017 0x0017 MMC Map 2 of 4 HCS12 Module Mapping Control Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0017 Reserved Read 0 0 0 0 0 0 0 0 Writ...

Page 29: ... 0 0 pag_sw1 pag_sw0 Write 0x001E 0x001E MEBI Map 2 of 3 HCS12 Multiplexed External Bus Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x001E INTCR Read IRQE IRQEN 0 0 0 0 0 0 Write 0x001F 0x001F INT Map 2 of 2 HCS12 Interrupt Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x001F HPRIO Read PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 Write 0x0020 0x002F DBG In...

Page 30: ... DBGCBL Read Bit 7 6 5 4 3 2 1 Bit 0 BKP1L Write 0x0030 0x0031 MMC Map 4 of 4 HCS12 Module Mapping Control Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0030 PPAGE Read 0 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 Write 0x0031 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0032 0x0033 MEBI Map 3 of 3 HCS12 Multiplexed External Bus Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...

Page 31: ...rite 0x003B RTICTL Read 0 RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 Write 0x003C COPCTL Read WCOP RSBCK 0 0 0 CR2 CR1 CR0 Write 0x003D FORBYP TEST ONLY Read RTIBYP COPBYP 0 PLLBYP 0 0 FCM 0 Write 0x003E CTCTL TEST ONLY Read TCTL7 TCTL6 TCTL5 TCTL4 TCLT3 TCTL2 TCTL1 TCTL0 Write 0x003F ARMCOP Read 0 0 0 0 0 0 0 0 Write Bit 7 6 5 4 3 2 1 Bit 0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0...

Page 32: ... 13 12 11 10 9 Bit 8 Write 0x0051 TC0 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0x0052 TC1 hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 0x0053 TC1 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0x0054 TC2 hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 0x0055 TC2 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0x0056 TC3 hi Read Bit 15 14 13 12 11 10 9 Bit 8 Write 0x0057 TC3 lo Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0x0058 TC4 h...

Page 33: ... Read 0 0 0 0 0 0 0 0 Write 0x0066 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0067 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0068 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0069 Reserved Read 0 0 0 0 0 0 0 0 Write 0x006A Reserved Read 0 0 0 0 0 0 0 0 Write 0x006B Reserved Read 0 0 0 0 0 0 0 0 Write 0x006C Reserved Read 0 0 0 0 0 0 0 0 Write 0x006D Reserved Read 0 0 0 0 0 0 0 0 Write 0x006E Reserved Read 0 0 0 0...

Page 34: ...e 0x0086 ATDSTAT0 Read SCF 0 ETORF FIFOR 0 CC2 CC1 CC0 Write 0x0087 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0088 ATDTEST0 Read 0 0 0 0 0 0 0 0 Write 0x0089 ATDTEST1 Read 0 0 0 0 0 0 0 SC Write 0x008A Reserved Read 0 0 0 0 0 0 0 0 Write 0x008B ATDSTAT1 Read CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 Write 0x008C Reserved Read 0 0 0 0 0 0 0 0 Write 0x008D ATDDIEN Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0x008E...

Page 35: ...Bit15 14 13 12 11 10 9 Bit8 Write 0x009F ATDDR7L Read Bit7 Bit6 0 0 0 0 0 0 Write 0x00A0 0x00C7 Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00A0 0x00C7 Reserved Read 0 0 0 0 0 0 0 0 Write 0x00C8 0x00CF SCI Asynchronous Serial Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00C8 SCIBDH Read 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 Write 0x00C9 SCIBDL Re...

Page 36: ...8 0x00DF SPI Serial Peripheral Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00D8 SPICR1 Read SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE Write 0x00D9 SPICR2 Read 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 Write 0x00DA SPIBR Read 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 Write 0x00DB SPISR Read SPIF 0 SPTEF MODF 0 0 0 0 Write 0x00DC Reserved Read 0 0 0 0 0 0 0 0 Write 0x00DD SPIDR Read...

Page 37: ...ead 0 0 0 0 0 0 0 0 Write 00E7 PWMPRSC Read 0 0 0 0 0 0 0 0 Write 00E8 PWMSCLA Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00E9 PWMSCLB Read Bit 7 6 5 4 3 2 1 Bit 0 Write 00EA PWMSCNTA Read 0 0 0 0 0 0 0 0 Write 00EB PWMSCNTB Read 0 0 0 0 0 0 0 0 Write 00EC PWMCNT0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0 0 0 0 0 0 0 0 00ED PWMCNT1 Read Bit 7 6 5 4 3 2 1 Bit 0 Write 0 0 0 0 0 0 0 0 00EE PWMCNT2 Read Bit 7 6 5 ...

Page 38: ...0 0 Write 0x0110 0x013F Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0110 0x003F Reserved Read 0 0 0 0 0 0 0 0 Write 0x0140 0x017F CAN Scalable Controller Area Network MSCAN 1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0140 CANCTL0 Read RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ Write 0x0141 CANCTL1 Read CANE CLKSRC LOOPB LISTEN 0 WUPM SLPAK INITA...

Page 39: ... Write 0x0154 0x0157 CANIDMR0 CANIDMR3 Read AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write 0x0158 0x015B CANIDAR4 CANIDAR7 Read AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write 0x015C 0x015F CANIDMR4 CANIDMR7 Read AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write 0x0160 0x016F CANRXFG Read FOREGROUND RECEIVE BUFFER see Table 1 2 Write 0x0170 0x017F CANTXFG Read FOREGROUND TRANSMIT BUFFER see Table 1 2 Write 1 Not available on th...

Page 40: ...IDR0 Write Standard ID Read ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 Write 0xxx11 Extended ID Read ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 CANxTIDR1 Write Standard ID Read ID2 ID1 ID0 RTR IDE 0 Write 0xxx12 Extended ID Read ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 CANxTIDR2 Write Standard ID Read Write 0xxx13 Extended ID Read ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR CANxTIDR3 Write Standard ID Read Write 0xxx14 0xxx...

Page 41: ...0244 PERT Read PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 Write 0x0245 PPST Read PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 Write 0x0246 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0247 MODRR Read 0 0 0 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 Write 0x0248 PTS Read 0 0 0 0 PTS3 PTS2 PTS1 PTS0 Write 0x0249 PTIS Read 0 0 0 0 PTIS3 PTIS2 PTIS1 PTIS0 Write 0x024A DDRS Read 0 0 0 0 DDRS3 DDRS2 DDRS1 DDRS...

Page 42: ...P4 RDRP3 RDRP2 RDRP1 RDRP0 Write 0x025C PERP Read PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 Write 0x025D PPSP Read PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0 Write 0x025E PIEP Read PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 Write 0x025F PIFP Read PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 Write 0x0260 Reserved Read 0 0 0 0 0 0 0 0 Write 0x0261 Reserved Read 0 0 0 0 0 0 0 0 Wri...

Page 43: ... PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIJ7 Write 0x0272 DDRAD Read DDRAD7 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0 Write 0x0273 RDRAD Read RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 Write 0x0274 PERAD Read PERAD7 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0 Write 0x0275 PPSAD Read PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 Write 0x0276 0x027F Reserved Read 0 0 0 0 0 0...

Page 44: ...tails Table 1 3 Assigned Part ID Numbers Device Mask Set Number Part ID 1 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set revision number including FAB transfers Bit 3 0 Minor non full mask set revision MC9S12C32 1L45J 3300 MC9S12C32 2L45J 3302 MC9S12C32 1M34C 3311 MC9S12GC16 2L45J 3302 MC9S12GC32 2L45J 3302 MC9S12GC32 1M34C 3311...

Page 45: ...D06 AN06 PAD05 AN05 PAD04 AN04 PAD03 AN03 PAD02 AN02 PAD01 AN01 PAD00 AN00 VSS2 VDD2 PA7 ADDR15 DATA15 PA6 ADDR14 DATA14 PA5 ADDR13 DATA13 PA4 ADDR12 DATA12 PA3 ADDR11 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 PA0 ADDR8 DATA8 PP4 KWP4 PW4 PP5 KWP5 PW5 PP7 KWP7 V DDX V SSX PM0 RXCAN PM1 TXCAN PM2 MISO PM3 SS PM4 MOSI PM5 SCK PJ6 KWJ6 PJ7 KWJ7 PP6 KWP6 ROMCTL PS3 PS2 PS1 TXD PS0 RXD V SSA V RL PW3 KW...

Page 46: ... 45 44 43 42 41 40 Signals shown in Bold italic are not available on the 48 pin package PP4 KWP4 PW4 PP5 KWP5 PW5 V DDX V SSX PM0 RXCAN PM1 TXCAN PM2 MISO PM3 SS PM4 MOSI PM5 SCK PS1 TXD PS0 RXD V SSA VRH VDDA PAD07 AN07 PAD06 AN06 PAD05 AN05 PAD04 AN04 PAD03 AN03 PAD02 AN02 PAD01 AN01 PAD00 AN00 PA2 PA1 PA0 XCLKS PE7 ECLK PE4 V SSR V DDR RESET V DDPLL XFC V SSPLL EXTAL XTAL V PP TEST IRQ PE1 XIRQ...

Page 47: ... 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 PP5 KWP5 PW5 V DDX V SSX PM0 RXCAN PM1 TXCAN PM2 MISO PM3 SS PM4 MOSI PM5 SCK PS1 TXD PS0 RXD V SSA PW0 IOC0 PT0 PW1 IOC1 PT1 PW2 IOC2 PT2 PW3 IOC3 PT3 VDD1 VSS1 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 MODC BKGD PB4 XCLKS PE7 ECLK PE4 V SSR V DDR RESET V DDPLL XFC V SSPLL EXTAL XTAL V PP TEST IRQ PE1 VRH VDDA PAD07 AN07 PAD06 AN06 PAD05 A...

Page 48: ...w PE2 R W VDDX PUCR Mode Dep1 Port E I O pin R W in expanded modes PE1 IRQ VDDX PUCR Up Port E input external interrupt pin PE0 XIRQ VDDX PUCR Up Port E input non maskable interrupt pin PA 7 3 ADDR 15 1 DATA 15 1 VDDX PUCR Disabled Port A I O pin and multiplexed address data PA 2 1 ADDR 10 9 DATA 10 9 VDDX PUCR Disabled Port A I O pin and multiplexed address data PA 0 ADDR 8 DATA 8 VDDX PUCR Disab...

Page 49: ...3 SS VDDX PERM PPSM Up Port M I O pin and SPI SS signal PM2 MISO VDDX PERM PPSM Up Port M I O pin and SPI MISO signal PM1 TXCAN VDDX PERM PPSM Up Port M I O pin and CAN transmit signal 2 PM0 RXCAN VDDX PERM PPSM Up Port M I O pin and CAN receive signal2 PS 3 2 VDDX PERS PPSS Up Port S I O pins PS1 TXD VDDX PERS PPSS Up Port S I O pin and SCI transmit signal PS0 RXD VDDX PERS PPSS Up Port S I O pin...

Page 50: ...eset an internal circuit drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal processing 1 3 4 3 TEST VPP Test Pin This pin is reserved for test and must be tied to VSS in all applications 1 3 4 4 XFC PLL Loop Filter Pin Dedicated pin used to create the PLL loop filter See CRG BUG for more detailed information PLL loop filter Please ask your Motorola represe...

Page 51: ...le This signal will assert when the CPU is not using the bus The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts low power oscillator is used or whether Pierce oscillator external clock circuitry is used The state of this pin is latched at the rising edge of RESET If the input is a logic low the EXTAL pin is configured for an external clock drive...

Page 52: ... ECLK frequency is equal to 1 2 the crystal frequency out of reset The ECLK pin is initially configured as ECLK output with stretch in all expanded modes The E clock output function depends upon the settings of the NECLK bit in the PEAR register the IVIS bit in the MODE register and the ESTR bit in the EBICTL register All clocks including the E clock are halted when the MCU is in stop mode It is p...

Page 53: ...er CCR is set and any interrupt is masked until MCU software enables it Because the XIRQ input is level sensitive it can be connected to a multiple source wired OR network This pin is always an input and can always be read There is an active pull up on this pin while in reset and immediately out of reset The pull up can be turned off by clearing PUPEE in the PUCR register 1 3 4 16 PAD 7 0 AN 7 0 P...

Page 54: ...d as inputs they can generate interrupts causing the MCU to exit stop or wait mode These pins are not available in the 48 pin package version nor in the 52 pin package version 1 3 4 21 PM5 SCK Port M I O Pin 5 PM5 is a general purpose input or output pin and also the serial clock pin SCK for the serial peripheral interface SPI 1 3 4 22 PM4 MOSI Port M I O Pin 4 PM4 is a general purpose input or ou...

Page 55: ...ompare pins IOC7 IOC5 1 3 4 31 PT 4 0 IOC 4 0 PW 4 0 Port T I O Pins 4 0 PT4 PT0 are general purpose input or output pins They can also be configured as the timer system input capture or output compare pins IOC n or as the PWM outputs PW n 1 3 5 Power Supply Pins 1 3 5 1 VDDX VSSX Power and Ground Pins for I O Drivers External power and ground for I O drivers Bypass requirements depend on how heav...

Page 56: ... characteristics and place them as close to the MCU as possible Bypass requirements depend on MCU pin load Table 1 6 Power and Ground Connection Summary Mnemonic Nominal Voltage V Description VDD1 VDD2 2 5 Internal power and ground generated by internal regulator These also allow an external source to supply the core VDD VSS voltages and bypass the internal voltage regulator In the 48 and 52 LQFP ...

Page 57: ...s exist for the device 1 5 1 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset The MODC MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation The states of the MODC MODB and MODA pins are latched into these bits on the rising edge of the reset signa...

Page 58: ...ogramming routine that updates parameters 1 5 2 1 Securing the Microcontroller Once the user has programmed the FLASH the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through resetting the part and through powering down the part Table 1 7 Mode Selection BKGD MODC PE6 MODB PE5 MODA PP6 ROMCTL ROMON Bit Mode Descr...

Page 59: ...single chip mode This invokes a program that verifies the erasure of the internal FLASH Once this program completes the user can erase and program the FLASH security bits to the unsecured state This is generally done through the BDM but the user could also change to expanded mode by writing the mode bits through the BDM and jumping to an external program again through BDM commands Note that if the...

Page 60: ...rupt Source CCR Mask Local Enable HPRIO Value to Elevate 0xFFFE 0xFFFF External reset power on reset or low voltage reset see CRG flags register to determine reset source None None 0xFFFC 0xFFFD Clock monitor fail reset None COPCTL CME FCME 0xFFFA 0xFFFB COP failure reset None COP rate select 0xFFF8 0xFFF9 Unimplemented instruction trap None None 0xFFF6 0xFFF7 SWI None None 0xFFF4 0xFFF5 XIRQ X Bi...

Page 61: ...9 Reserved 0xFFC6 0xFFC7 CRG PLL lock I bit PLLCR LOCKIE 0x00C6 0xFFC4 0xFFC5 CRG self clock mode I bit PLLCR SCMIE 0x00C4 0xFFBA to 0xFFC3 Reserved 0xFFB8 0xFFB9 FLASH I bit FCNFG CCIE CBEIE 0x00B8 0xFFB6 0xFFB7 CAN wake up 1 I bit CANRIER WUPIE 0x00B6 0xFFB4 0xFFB5 CAN errors1 I bit CANRIER CSCIE OVRIE 0x00B4 0xFFB2 0xFFB3 CAN receive1 I bit CANRIER RXFIE 0x00B2 0xFFB0 0xFFB1 CAN transmit1 I bit...

Page 62: ... after reset The RAM array is not automatically initialized out of reset NOTE For devices assembled in 48 pin or 52 pin LQFP packages all non bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 1 5 for affected pins 1 7 Device Specific Information and Module Dependencies 1 7 1 PPAGE External paging is not supported on thes...

Page 63: ...revent a floating input thereby preventing unnecessary current flow at the input stage To prevent unnecessary current flow in production package options the states of DDRK and PUPKE should not be changed by software Table 1 11 Device Specific Flash PAGE Mapping Device PAGE PAGE Visible with PPAGE Contents MC9S12GC16 3F 01 03 05 07 09 35 37 39 3B 3D 3F MC9S12C32 MC9S12GC32 3E 00 02 04 06 08 0A 0C 0...

Page 64: ...Converter In the 48 and 52 pin package versions the VRL pad is bonded internally to the VSSA pin 1 7 8 MODRR Register Port T And Port P Mapping The MODRR register within the PIM allows for mapping of PWM channels to port T in the absence of port P pins for the low pin count packages For the 80QFP package option it is recommended not to use MODRR since this is intended to support PWM channel availa...

Page 65: ... C6 C7 C5 and Q1 and the connection area to the MCU Central power input should be fed in at the VDDA VSSA pins Table 1 12 Recommended Component Values Component Purpose Type Value C1 VDD1 filter capacitor Ceramic X7R 220nF 470nF 1 1 In 48LQFP and 52LQFP package versions VDD2 is not available Thus 470nF must be connected to VDD1 C2 VDDR filter capacitor X7R tantalum 100nF C3 VDDPLL filter capacitor...

Page 66: ...Chapter 1 MC9S12C and MC9S12GC Device Overview MC9S12C128 66 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 Figure 1 15 Recommended PCB Layout 48 LQFP Colpitts Oscillator ...

Page 67: ...Chapter 1 MC9S12C and MC9S12GC Device Overview MC9S12C128 Freescale Semiconductor MC9S12C Family MC9S12GC Family 67 Rev 01 24 Figure 1 16 Recommended PCB Layout 52 LQFP Colpitts Oscillator ...

Page 68: ...Chapter 1 MC9S12C and MC9S12GC Device Overview MC9S12C128 68 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 Figure 1 17 Recommended PCB Layout 80 QFP Colpitts Oscillator ...

Page 69: ...Chapter 1 MC9S12C and MC9S12GC Device Overview MC9S12C128 Freescale Semiconductor MC9S12C Family MC9S12GC Family 69 Rev 01 24 Figure 1 18 Recommended PCB Layout for 48 LQFP Pierce Oscillator ...

Page 70: ...Chapter 1 MC9S12C and MC9S12GC Device Overview MC9S12C128 70 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 Figure 1 19 Recommended PCB Layout for 52 LQFP Pierce Oscillator ...

Page 71: ...Chapter 1 MC9S12C and MC9S12GC Device Overview MC9S12C128 Freescale Semiconductor MC9S12C Family MC9S12GC Family 71 Rev 01 24 Figure 1 20 Recommended PCB Layout for 80QFP Pierce Oscillator ...

Page 72: ...Chapter 1 MC9S12C and MC9S12GC Device Overview MC9S12C128 72 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 73: ...PWM module external interrupt sources available Port J pins can be used as external interrupt sources and standard I O s The following I O pin configurations can be selected Available on all I O pins Input output selection Drive strength reduction Enable and select of pull resistors Available on all Port P and Port J pins Interrupt enable and status flags The implementation of the Port Integration...

Page 74: ...IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 Port P PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 Port S PS0 PS1 PM2 PM3 PM4 PM5 PM0 PM1 RXD TXD RXCAN TXCAN MISO MOSI SCK SS SCI CAN SPI Port J PJ7 Port Integration Module IRQ Logic Interrupt Logic Port B PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Port A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Port E PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 ADDR8 DATA8 ADDR9 DATA9 ADDR10 DATA10 ADDR11 DATA11 ADDR12 D...

Page 75: ...n Module PIM9C32 Block Description Freescale Semiconductor MC9S12C Family MC9S12GC Family 75 Rev 01 24 when mapping PWM channels to Port T in an 80QFP option the associated PWM channels are then mapped to both Port P and Port T ...

Page 76: ...led in MODRR register GPIO IOC 7 0 Standard timer channels GPIO General purpose I O Port S PS3 GPIO General purpose I O PS2 GPIO General purpose I O PS1 TXD Serial communication interface transmit pin GPIO General purpose I O PS0 RXD Serial communication interface receive pin GPIO General purpose I O Port M PM5 SCK SPI clock PM4 MOSI SPI transmit pin PM3 SS SPI slave select line PM2 MISO SPI recei...

Page 77: ...ddress Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PTT R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W TIM IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 PWM PWM4 PWM3 PWM2 PWM1 PWM0 0x0001 PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W 0x0002 DDRT R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W 0x0003 RDRT R RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 W 0x0004 PERT R PERT7 PERT6 PERT5 PERT4 PERT3 ...

Page 78: ...x000F Reserved R 0 0 0 0 0 0 0 0 W 0x0010 PTM R 0 0 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 W MSCAN SPI SCK MOSI SS MISO TXCAN RXCAN 0x0011 PTIM R 0 0 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 W 0x0012 DDRM R 0 0 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 W 0x0013 RDRM R 0 0 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 W 0x0014 PERM R 0 0 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 W 0x0015 PPSM R 0 0 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0...

Page 79: ... 0x002A DDRJ R DDRJ7 DDRJ6 0 0 0 0 0 0 W 0x002B RDRJ R RDRJ7 RDRJ6 0 0 0 0 0 0 W 0x002C PERJ R PERJ7 PERJ6 0 0 0 0 0 0 W 0x002D PPSJ R PPSJ7 PPSJ6 0 0 0 0 0 0 W 0x002E PIEJ R PIEJ7 PIEJ6 0 0 0 0 0 0 W 0x002F PIFJ R PIFJ7 PIFJ6 0 0 0 0 0 0 W 0x0030 PTAD R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W 0x0031 PTIAD R PTIAD7 PTIAD6 PTIAD5 PTIAD4 PTIAD3 PTIAD2 PTIAD1 PTIAD0 W 0x0032 DDRAD R DDRAD7 ...

Page 80: ...ister read Table 2 2 Pin Configuration Summary DDR IO RDR PE PS IE 1 1 Applicable only on ports P and J Function Pull Device Interrupt 0 X X 0 X 0 Input Disabled Disabled 0 X X 1 0 0 Input Pull up Disabled 0 X X 1 1 0 Input Pull down Disabled 0 X X 0 0 1 Input Disabled Falling edge 0 X X 0 1 1 Input Disabled Rising edge 0 X X 1 0 1 Input Pull up Falling edge 0 X X 1 1 1 Input Pull down rising edge...

Page 81: ...needs to be configured Module Base 0x0000 7 6 5 4 3 2 1 0 R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W TIM IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 PWM PWM4 PWM3 PWM2 PWM1 PWM0 Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 2 3 Port T I O Register PTT Table 2 3 Port T 4 0 Pin Functionality Configurations 1 1 All fields in the that are not shaded are standard use cases MODRR x PWME x TIMEN x ...

Page 82: ... 7 6 5 4 3 2 1 0 R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W Reset 0 0 0 0 0 0 0 0 Figure 2 5 Port T Data Direction Register DDRT Table 2 5 DDRT Field Descriptions Field Description 7 0 DDRT 7 0 Data Direction Port T This register configures each port T pin as either input or output The standard TIM PWM modules forces the I O state to be an output for each standard TIM PWM module port asso...

Page 83: ... drive strength of each port T output pin as either full or reduced If the port is used as input this bit is ignored 0 Full drive strength at output 1 Associated pin drives at about 1 3 of the full drive strength Module Base 0x0004 7 6 5 4 3 2 1 0 R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W Reset 0 0 0 0 0 0 0 0 Figure 2 7 Port T Pull Device Enable Register PERT Table 2 7 PERT Field Descri...

Page 84: ...T This register selects whether a pull down or a pull up device is connected to the pin 0 A pull up device is connected to the associated port T pin if enabled by the associated bit in register PERT and if the port is used as input 1 A pull down device is connected to the associated port T pin if enabled by the associated bit in register PERT and if the port is used as input Module Base 0x0007 7 6...

Page 85: ...if the receiver is enabled Please refer to SCI Block User Guide for details 2 3 2 2 2 Port S Input Register PTIS Read Anytime Write Never writes to this register have no effect Module Base 0x0008 7 6 5 4 3 2 1 0 R 0 0 0 0 PTS3 PTS2 PTS1 PTS0 W SCI TXD RXD Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 2 10 Port S I O Register PTS Module Base 0x0009 7 6 5 4 3 2 1 0 R 0 0 0 0 PTIS3 PTIS2 PTI...

Page 86: ... S This register configures each port S pin as either input or output If the associated SCI transmit or receive channel is enabled this register has no effect on the pins The pin is forced to be an output if the SCI transmit channel is enabled it is forced to be an input if the SCI receive channel is enabled The DDRS bits revert to controlling the I O direction of a pin when the associated channel...

Page 87: ...t S output pin as either full or reduced If the port is used as input this bit is ignored 0 Full drive strength at output 1 Associated pin drives at about 1 3 of the full drive strength Module Base 0x000C 7 6 5 4 3 2 1 0 R 0 0 0 0 PERS3 PERS2 PERS1 PERS0 W Reset 0 0 0 0 1 1 1 1 Unimplemented or Reserved Figure 2 14 Port S Pull Device Enable Register PERS Table 2 13 PERS Field Descriptions Field De...

Page 88: ... is connected to the associated port S pin if enabled by the associated bit in register PERS and if the port is used as input or as wired or output 1 A pull down device is connected to the associated port S pin if enabled by the associated bit in register PERS and if the port is used as input Module Base 0x000E 7 6 5 4 3 2 1 0 R 0 0 0 0 WOMS3 WOMS2 WOMS1 WOMS0 W Reset 0 0 0 0 0 0 0 0 Unimplemented...

Page 89: ... for details 2 3 2 3 2 Port M Input Register PTIM Read Anytime Write Never writes to this register have no effect Module Base 0x0010 7 6 5 4 3 2 1 0 R 0 0 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 W MSCAN SPI SCK MOSI SS MISO TXCAN RXCAN Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 2 17 Port M I O Register PTM Module Base 0x0011 7 6 5 4 3 2 1 0 R 0 0 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 W Reset Unimp...

Page 90: ...abled the SPI and MSCAN modules determines the pin directions Please refer to the SPI and MSCAN Block User Guides for details If the associated SCI or MSCAN transmit or receive channels are enabled this register has no effect on the pins The pins are forced to be outputs if the SCI or MSCAN transmit channels are enabled they are forced to be inputs if the SCI or MSCAN receive channels are enabled ...

Page 91: ... output pin as either full or reduced If the port is used as input this bit is ignored 0 Full drive strength at output 1 Associated pin drives at about 1 3 of the full drive strength Module Base 0x0014 7 6 5 4 3 2 1 0 R 0 0 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 W Reset 0 0 1 1 1 1 1 1 Unimplemented or Reserved Figure 2 21 Port M Pull Device Enable Register PERM Table 2 19 PERM Field Descriptions Fie...

Page 92: ...ce is connected to the associated port M pin if enabled by the associated bit in register PERM and if the port is used as input or as wired or output 1 A pull down device is connected to the associated port M pin if enabled by the associated bit in register PERM and if the port is used as input Module Base 0x0016 7 6 5 4 3 2 1 0 R 0 0 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 W Reset 0 0 0 0 0 0 0 0 Uni...

Page 93: ... 4 2 Port P Input Register PTIP Read Anytime Write Never writes to this register have no effect This register always reads back the status of the associated pins This can be also used to detect overload or short circuit conditions on output pins Module Base 0x0018 7 6 5 4 3 2 1 0 R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W PWM PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Reset 0 0 0 0 0 0 0 0 Figure 2 24 Port P ...

Page 94: ...n as either input or output 0 Associated pin is configured as input 1 Associated pin is configured as output Note Due to internal synchronization circuits it can take up to 2 bus cycles until the correct value is read on PTP or PTIP registers when changing the DDRP register Module Base 0x001B 7 6 5 4 3 2 1 0 R RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 W Reset 0 0 0 0 0 0 0 0 Figure 2 27 Port...

Page 95: ...ull down device is disabled 1 Either a pull up or pull down device is enabled Module Base 0x001D 7 6 5 4 3 2 1 0 R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W Reset 0 0 0 0 0 0 0 0 Figure 2 29 Port P Polarity Select Register PPSP Table 2 25 PPSP Field Descriptions Field Description 7 0 PPSP 7 0 Pull Select Port P This register serves a dual purpose by selecting the polarity of the active int...

Page 96: ...ernal interrupt associated with port P 0 Interrupt is disabled interrupt flag masked 1 Interrupt is enabled Module Base 0x001F 7 6 5 4 3 2 1 0 R PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W Reset 0 0 0 0 0 0 0 0 Figure 2 31 Port P Interrupt Flag Register PIFP Table 2 27 PIFP Field Descriptions Field Description 7 0 PIFP 7 0 Interrupt Flags Port P Each flag is set by an active edge on the asso...

Page 97: ...value at the pins is read 2 3 2 5 2 Port J Input Register PTIJ Read Anytime Write Never writes to this register have no effect This register always reads back the status of the associated pins This can be used to detect overload or short circuit conditions on output pins Module Base 0x0028 7 6 5 4 3 2 1 0 R PTJ7 PTJ6 0 0 0 0 0 0 W Reset 0 0 Unimplemented or Reserved Figure 2 32 Port J I O Register...

Page 98: ...ut or output DDRJ 7 6 Data Direction Port J 0 Associated pin is configured as input 1 Associated pin is configured as output Note Due to internal synchronization circuits it can take up to 2 bus cycles until the correct value is read on PTJ or PTIJ registers when changing the DDRJ register Module Base 0x002B 7 6 5 4 3 2 1 0 R RDRJ7 RDRJ6 0 0 0 0 0 0 W Reset 0 0 Unimplemented or Reserved Figure 2 3...

Page 99: ... is disabled 1 Either a pull up or pull down device is enabled Module Base 0x002D 7 6 5 4 3 2 1 0 R PPSJ7 PPSJ6 0 0 0 0 0 0 W Reset 0 0 Unimplemented or Reserved Figure 2 37 Port J Polarity Select Register PPSJ Table 2 31 PPSJ Field Descriptions Field Description 7 6 PPSJ 7 6 Reduced Drive Port J This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as ...

Page 100: ... external interrupt associated with port J 0 Interrupt is disabled interrupt flag masked 1 Interrupt is enabled Module Base 0x002F 7 6 5 4 3 2 1 0 R PIFJ7 PIFJ6 0 0 0 0 0 0 W Reset 0 0 Unimplemented or Reserved Figure 2 39 Port J Interrupt Flag Register PIFJ Table 2 33 PIFJ Field Descriptions Field Description 7 6 PIFJ 7 6 Interrupt Flags Port J Each flag is set by an active edge on the associated...

Page 101: ...read 2 3 2 6 2 Port AD Input Register PTIAD Read Anytime Write Never writes to this register have no effect This register always reads back the status of the associated pins This can be used to detect overload or short circuit conditions on output pins Module Base 0x0030 7 6 5 4 3 2 1 0 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W Reset 0 0 0 0 0 0 0 0 Figure 2 40 Port AD I O Register PTAD ...

Page 102: ... 0 as either input or output 0 Associated pin is configured as input 1 Associated pin is configured as output Note Due to internal synchronization circuits it can take up to 2 bus cycles until the correct value is read on PTAD or PTIAD registers when changing the DDRAD register Module Base 0x0033 7 6 5 4 3 2 1 0 R RDRAD7 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0 W Reset 0 0 0 0 0 0 0 0 Figu...

Page 103: ... port is used as output Out of reset no pull device is enabled It is not possible to enable pull devices when a associated ATD channel is enabled simultaneously 0 Pull up or pull down device is disabled 1 Either a pull up or pull down device is enabled Module Base 0x0035 7 6 5 4 3 2 1 0 R PPSAD7 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0 W Reset 0 0 0 0 0 0 0 0 Figure 2 45 Port AD Polarity S...

Page 104: ... the pin if the port is used as a general purpose I O Writing to this register has only an effect on the pin if the port is used as general purpose output When reading this address the value of the pins are returned if the data direction register bits are set to 0 If the data direction register bits are set to 1 the contents of the I O register is returned This is independent of any other configur...

Page 105: ...s module if so configured by MODRR During reset port T pins are configured as high impedance inputs 2 4 2 2 Port S This port is associated with the serial SCI module Port S pins PS 3 0 can be used either for general purpose I O or with the SCI subsystem During reset port S pins are configured as inputs with pull up 2 4 2 3 Port M This port is associated with the MSCAN and SPI module Port M pins PM...

Page 106: ...erated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set This external interrupt feature is capable to wake up the CPU when it is in STOP or WAIT mode A digital filter on each pin prevents pulses Figure 2 48 shorter than a specified time from generating an interrupt The minimum time varies over process conditions temperature and voltage Fig...

Page 107: ...iven general purpose I O s During reset port J pins are configured as inputs Port J offers 2 I O ports with the same interrupt features as on port P 2 4 3 Port A B E and BKGD Pin All port and pin logic is located in the core module Please refer to S12_mebi Block User Guide for details 2 4 4 External Pin Descriptions All ports start up as general purpose inputs on reset 2 4 5 Low Power Options 2 4 ...

Page 108: ...y have extra transitions during the write access Initialize the port data register before enabling the outputs Power consumption will increase the more the voltages on general purpose input pins deviate from the supply voltages towards mid range because the digital input buffers operate in the linear region Table 2 39 Port Reset State Summary Port Reset States Data Direction Pull Mode Reduced Driv...

Page 109: ...ternal space Internal buses between the core and memories and between the core and peripherals is controlled in this module The memory expansion is generated in this module MMC MODE INFORMATION REGISTERS CPU WRITE DATA BUS CPU ADDRESS BUS CPU CONTROL STOP WAIT ADDRESS DECODE CPU READ DATA BUS EBI ALTERNATE ADDRESS BUS EBI ALTERNATE WRITE DATA BUS EBI ALTERNATE READ DATA BUS SECURITY CLOCKS RESET R...

Page 110: ... into the system on a chip SoC 3 1 2 Modes of Operation Some of the registers operate differently depending on the mode of operation i e normal expanded wide special single chip etc This is best understood from the register descriptions 3 2 External Signal Description All interfacing with the MMC sub block is done within the core it has no external signals 3 3 Memory Map and Register Definition A ...

Page 111: ...nductor MC9S12C Family MC9S12GC Family 111 Rev 01 24 0x0017 Reserved 0x001C Memory Size Register 0 MEMSIZ0 R 0x001D Memory Size Register 1 MEMSIZ1 R 0x0030 Program Page Index Register PPAGE R W 0x0031 Reserved Table 3 1 MMC Memory Map continued Address Offset Register Access ...

Page 112: ...G13 REG12 REG11 0 0 0 W 0x0012 INITEE R EE15 EE14 EE13 EE12 EE11 0 0 EEON W 0x0013 MISC R 0 0 0 0 EXSTR1 EXSTR0 ROMHM ROMON W 0x0014 MTSTO R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0017 MTST1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001C MEMSIZ0 R REG_SW0 0 EEP_SW1 EEP_SW0 0 RAM_SW2 RAM_SW1 RAM_SW0 W 0x001D MEMSIZ1 R ROM_SW1 ROM_SW0 0 0 0 0 PAG_SW1 PAG_SW0 W 0x0030 PPAGE R 0 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 W 0x0031 Rese...

Page 113: ... Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R RAM15 RAM14 RAM13 RAM12 RAM11 0 0 RAMHAL W Reset 0 0 0 0 1 0 0 1 Unimplemented or Reserved Figure 3 3 Initialization of Internal RAM Position Register INITRM Table 3 2 INITRM Field Descriptions Field Description 7 3 RAM 15 11 Internal RAM Map Position These bits determine the upper five bits of the base address for th...

Page 114: ...any 2K byte space within the first 32K bytes of the system s address space Module Base 0x0011 Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R 0 REG14 REG13 REG12 REG11 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 4 Initialization of Internal Registers Position Register INITRG Table 3 3 INITRG Field Descriptions Field Description 6 3 REG 14 11 Int...

Page 115: ...thin the on chip system memory map Module Base 0x0012 Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R EE15 EE14 EE13 EE12 EE11 0 0 EEON W Reset1 1 The reset state of this register is controlled at chip integration Please refer to the device overview section to determine the actual reset state of this register Unimplemented or Reserved Figure 3 5 Initialization of In...

Page 116: ...2 EXSTR 1 0 External Access Stretch Bits 1 and 0 Write once in normal and emulation modes and anytime in special modes This two bit field determines the amount of clock stretch on accesses to the external address space as shown in Table 3 6 In single chip and peripheral modes these bits have no meaning or effect 1 ROMHM FLASH EEPROM or ROM Only in Second Half of Memory Map Write once in normal and...

Page 117: ...al test purposes Table 3 6 External Stretch Bit Definition Stretch Bit EXSTR1 Stretch Bit EXSTR0 Number of E Clocks Stretched 0 0 0 0 1 1 1 0 2 1 1 3 Module Base 0x0014 Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 7 Reserved Test Register 0 MTST0 Module Base 0x0017 Starting address locatio...

Page 118: ...mented or Reserved Figure 3 9 Memory Size Register 0 MEMSIZ0 Table 3 7 MEMSIZ0 Field Descriptions Field Description 7 REG_SW0 Allocated System Register Space 0 Allocated system register space size is 1K byte 1 Allocated system register space size is 2K byte 5 4 EEP_SW 1 0 Allocated System EEPROM Memory Space The allocated system EEPROM memory space size is as given in Table 3 8 2 RAM_SW 2 0 Alloca...

Page 119: ...oundary which are configured at system integration This register allows read visibility to the state of these switches 011 8K bytes 8K bytes RAM 15 13 0x0000 100 10K bytes 16K bytes 2 RAM 15 14 0x1800 101 12K bytes 16K bytes 2 RAM 15 14 0x1000 110 14K bytes 16K bytes 2 RAM 15 14 0x0800 111 16K bytes 16K bytes RAM 15 14 0x0000 1 The RAM Reset BASE Address is based on the reset value of the INITRM r...

Page 120: ...ocated system FLASH or ROM physical memory space is as given in Table 3 11 1 0 PAG_SW 1 0 Allocated Off Chip FLASH or ROM Memory Space The allocated off chip FLASH or ROM memory space size is as given in Table 3 12 Table 3 11 Allocated FLASH ROM Physical Memory Space rom_sw1 rom_sw0 Allocated FLASH or ROM Space 00 0K byte 01 16K bytes 10 48K bytes 1 11 64K bytes 1 NOTES 1 The ROMHM software bit in...

Page 121: ...ow located from 0x8000 to 0xBFFF as defined in Table 3 14 CALL and RTC instructions have special access to read and write this register without using the address bus NOTE Normal writes to this register take one cycle to go into effect Writes to this register using the special access of the CALL and RTC instructions will be complete before the end of the associated instruction Module Base 0x0030 St...

Page 122: ...MC decodes the address information determines whether the internal core register or firmware space the peripheral space or a memory register or array space is being addressed and generates the correct select signal This decoding operation also interprets the mode of operation of the system and the state of the mapping control registers in order to generate the proper select The MMC also generates ...

Page 123: ...d become external accesses In special peripheral mode the first 16 registers associated with bus expansion are removed from the on chip memory map PORTA PORTB DDRA DDRB PORTE DDRE PEAR MODE PUCR RDRIV and the EBI reserved registers In emulation modes if the EMK bit in the MODE register see MEBI block description chapter is set the data and data direction registers for port K are removed from the o...

Page 124: ...witches pag_sw1 pag_sw0 at the core boundary The options available to the integrator are as given in Table 3 16 this table matches Table 3 12 but is repeated here for easy reference Based upon the system configuration the program page window will consider its access to be either internal or external as defined in Table 3 17 NOTE The partitioning as defined in Table 3 17 applies only to the allocat...

Page 125: ...The PPAGE value controls which of the 64 possible pages is visible through the 16K byte expansion window in the 64K byte memory map Execution then begins at the address of the called subroutine During the execution of a CALL instruction the CPU Writes the old PPAGE value into an internal temporary register and writes the new instruction supplied PPAGE value into the PPAGE register Calculates the a...

Page 126: ...will be output on XAB19 14 respectively port K bits 5 0 when the system is addressing within the physical program page window address space 0x8000 0xBFFF and is in an expanded mode When addressing anywhere else within the physical address space outside of the paging space the XAB19 14 signals will be assigned a constant value based upon the physical address space selected In addition the active lo...

Page 127: ...HM ECS XAB19 14 0x0000 0x3FFF N A N A 1 0x3D 0x4000 0x7FFF N A 0 0 0x3E N A 1 1 0x8000 0xBFFF External N A 1 PIX 5 0 Internal N A 0 0xC000 0xFFFF N A N A 0 0x3F Table 3 21 64K Byte Physical FLASH ROM Allocated Address Space Page Window Access ROMHM ECS XAB19 14 0x0000 0x3FFF N A 0 0 0x3D N A 1 1 0x4000 0x7FFF N A 0 0 0x3E N A 1 1 0x8000 0xBFFF External N A 1 PIX 5 0 Internal N A 0 0xC000 0xFFFF N ...

Page 128: ...ce is given in Figure 3 12 Figure 3 12 Memory Paging Example 1M Byte On Chip FLASH ROM 64K Allocation These 16K FLASH ROM pages accessible from 0x0000 to 0x7FFF if selected by the ROMHM bit in the MISC register NORMAL SINGLE CHIP ONE 16K FLASH ROM PAGE ACCESSIBLE AT A TIME SELECTED BY PPAGE 0 TO 63 0x0000 0x8000 0xFF00 0xFFFF 0x4000 0xC000 59 62 63 60 61 62 63 0 1 2 3 61 16K FLASH UNPAGED 16K FLAS...

Page 129: ...epending upon the system operating mode and the state of bits within the control registers of the MEBI the internal 16 bit read and write data operations will be represented in 8 bit or 16 bit accesses externally Using control information from other blocks within the system the MEBI will determine the appropriate type of data access to be generated 4 1 1 Features The block name includes these dist...

Page 130: ...7 0 A 15 8 D 15 8 D 7 0 Port K Port A PB 7 0 A 7 0 D 7 0 Port B Port E BKGD REGS EXT BUS I F CTL Addr 19 0 Data 15 0 Control Internal Bus ECLK CTL IRQ CTL ADDR ADDR DATA ADDR DATA PIPE CTL CPU pipe info IRQ interrupt XIRQ interrupt BDM tag info IPIPE1 MODB CLKTO IPIPE0 MODA ECLK LSTRB TAGLO R W TAG CTL Control signal s Data signal unidirectional Data bus unidirectional Data bus bidirectional Data ...

Page 131: ...BKGD pin There is no external expansion bus after reset in this mode Emulation expanded wide mode Developers use this mode for emulation systems in which the users target application is normal expanded wide mode Emulation expanded narrow mode Developers use this mode for emulation systems in which the users target application is normal expanded narrow mode Special test mode Ports A and B are confi...

Page 132: ...exed during ECLK high in expanded narrow modes and narrow accesses in wide modes Direction of data transfer is generally indicated by R W PB7 A7 D7 thru PB0 A0 D0 PB7 PB0 General purpose I O pins see PORTB and DDRB registers A7 A0 Low order address lines multiplexed during ECLK low Outputs except in special peripheral mode where they are inputs from an external tester system D7 D0 Low order bidire...

Page 133: ...dicates valid data on D7 D0 SZ8 In special peripheral mode this pin is an input indicating the size of the data transfer 0 16 bit 1 8 bit TAGLO In expanded wide mode or emulation narrow modes when instruction tagging is on and low strobe is enabled a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue PE2 R W PE2 General purpose I O pin see PO...

Page 134: ... R W 0x000B Mode Register MODE R W 0x000C Pull Control Register PUCR R W 0x000D Reduced Drive Register RDRIV R W 0x000E External Bus Interface Control Register EBICTL R W 0x000F Reserved R 0x001E IRQ Control Register IRQCR R W 0x00032 Port K Data Register PORTK R W 0x00033 Data Direction Register K DDRK R W Module Base 0x0000 Starting address location affected by INITRG register setting 7 6 5 4 3 ...

Page 135: ...e when register is in the map Write Anytime when register is in the map Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7 through D0 respectively When this port is not used for external addresses such as in single chip mode these pins can be used as general purpose I O Data direction register B DDRB determines the primary direction of each pin D...

Page 136: ...for reads of the corresponding PORTA register If the DDR bit is 0 input the buffered pin input state is read If the DDR bit is 1 output the associated port data register bit state is read This register is not in the on chip memory map in expanded and special peripheral modes Therefore these accesses will be echoed externally It is reset to 0x00 so the DDR does not override the three state control ...

Page 137: ...for reads of the corresponding PORTB register If the DDR bit is 0 input the buffered pin input state is read If the DDR bit is 1 output the associated port data register bit state is read This register is not in the on chip memory map in expanded and special peripheral modes Therefore these accesses will be echoed externally It is reset to 0x00 so the DDR does not override the three state control ...

Page 138: ...Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 7 Reserved Register Module Base 0x0006 Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 8 Reserved Register Module Base 0x0007 Starting add...

Page 139: ...ermines the source of data for a read of PORTE Some of these pins have software selectable pull resistors IRQ and XIRQ can only be pulled up whereas the polarity of the PE7 PE4 PE3 and PE2 pull resistors are determined by chip integration Please refer to the device overview chapter Signal Property Summary to determine the polarity of these resistors A single control bit enables the pull devices fo...

Page 140: ...The value in a DDR bit also affects the source of data for reads of the corresponding PORTE register If the DDR bit is 0 input the buffered pin input state is read If the DDR bit is 1 output the associated port data register bit state is read This register is not in the on chip memory map in expanded and special peripheral modes Therefore these accesses will be echoed externally Also it is not in ...

Page 141: ...ntrol function and the other bits of port E are configured for general purpose I O As the reset vector is located in external memory the E clock is required for this access R W is only needed by the system when there are external writable resources If the normal expanded system needs any other bus control signals PEAR would need to be written before any access that needed the additional signals In...

Page 142: ...rnal E clock is available as an output in all modes 3 LSTRE Low Strobe LSTRB Enable Normal write once Emulation write never Special write anytime 0 The associated pin port E bit 3 is a general purpose I O pin 1 The associated pin port E bit 3 is configured as the LSTRB bus control output If BDM tagging is enabled TAGLO is multiplexed in on the rising edge of ECLK and LSTRB is driven out on the fal...

Page 143: ...s shown to system configuration features Changes to bits in the MODE register are delayed one cycle after the write This register is not in the on chip memory map in expanded and special peripheral modes Therefore these accesses will be echoed externally Module Base 0x000B Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R MODC MODB MODA 0 IVIS 0 EMK EME W Reset Specia...

Page 144: ... write once Emulation write never Special write anytime 0 No visibility of internal bus operations on external bus 1 Internal bus operations are visible on external bus 1 EMK Emulate Port K Normal write once Emulation write never Special write anytime 0 PORTK and DDRK are in the memory map so port K can be used for general purpose I O 1 If in any expanded mode PORTK and DDRK are removed from the m...

Page 145: ...de MODx Write Capability 0 0 0 Special single chip MODC MODB and MODA write anytime but not to 110 2 2 If you are in a special single chip or special test mode and you write to this register changing to normal single chip mode then one allowed write to this register remains If you write to normal expanded or emulation mode then no writes remain 0 0 1 Emulation narrow No write 0 1 0 Special test MO...

Page 146: ...icular port This register is not in the on chip memory map in expanded and special peripheral modes Therefore these accesses will be echoed externally Table 4 9 PUCR Field Descriptions Field Description 7 PUPKE Pull resistors Port K Enable 0 Port K pull resistors are disabled 1 Enable pull resistors for port K input pins 4 PUPEE Pull resistors Port E Enable 0 Port E pull resistors on bits 7 4 0 ar...

Page 147: ...enabled 1 RDPB Reduced Drive of Port B 0 All port B output pins have full drive enabled 1 All port B output pins have reduced drive enabled 0 RDPA Reduced Drive of Ports A 0 All port A output pins have full drive enabled 1 All port A output pins have reduced drive enabled Module Base 0x000E Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 ESTR W Reset P...

Page 148: ...Reserved Figure 4 17 Reserved Register Module Base 0x001E Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R IRQE IRQEN 0 0 0 0 0 0 W Reset 0 1 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 18 IRQ Control Register IRQCR Table 4 12 IRQCR Field Descriptions Field Description 7 IRQE IRQ Select Edge Sensitive Only Special modes read or write anytime Normal and Emulation m...

Page 149: ... Port K Data Register PORTK Table 4 13 PORTK Field Descriptions Field Description 7 Port K Bit 7 Port K Bit 7 This bit is used as an emulation chip select signal for the emulation of the internal memory expansion or as general purpose I O depending upon the state of the EMK bit in the MODE register While this bit is used as a chip select the external bit will return to its de asserted state VDD fo...

Page 150: ...e low half of the data bus and the data for address 1 is on the high half of the data bus This is summarized in Table 4 15 Module Base 0x0033 Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure 4 20 Port K Data Direction Register DDRK Table 4 14 EBICTL Field Descriptions Field Description 7 0 DDRK Data Direction Por...

Page 151: ...riod of stretching throughout the stretched E high time NOTE The address portion of the bus cycle is not stretched 4 4 3 Modes of Operation The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset Table 4 16 The MODC MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation The states o...

Page 152: ...he bus can be changed after reset on a per mode basis 4 4 3 1 Normal Operating Modes These modes provide three operating configurations Background debug is available in all three modes but must first be enabled for some operations by means of a BDM background command then activated 4 4 3 1 1 Normal Single Chip Mode There is no external expansion bus in this mode All pins of Ports A B and E are con...

Page 153: ...pose input because the LSTRB function is not needed in all expanded wide applications The Port E bit 4 pin is initially configured as ECLK output with stretch The E clock output function depends upon the settings of the NECLK bit in the PEAR register the IVIS bit in the MODE register and the ESTR bit in the EBICTL register The E clock is available for use in external select decode logic or as a co...

Page 154: ...trol output functions rather than general purpose I O Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted 4 4 3 1 5 Emulation Expanded Narrow Mode Expanded narrow modes are intended to allow connection of single 8 bit external memory devices for lower cost systems that do not need the performance of a full 16 bit external data bus Accesses to int...

Page 155: ...ode The pins associated with Port E bits 6 5 3 and 2 cannot be configured for their alternate functions IPIPE1 IPIPE0 LSTRB and R W while the MCU is in single chip modes In single chip modes the associated control bits PIPOE LSTRE and RDWE are reset to zero Writing the opposite value into these bits in single chip mode does not change the operation of the associated Port E pins Port E bit 4 can be...

Page 156: ... remain high data will maintain its previous state and address and LSTRB pins will be updated with the internal value During CPU no access cycles when the BDM is not driving R W will remain high and address data and the LSTRB pins will remain at their previous state NOTE When the system is operating in a secure mode internal visibility is not available i e IVIS 1 has no effect Also the IPIPE signa...

Page 157: ...b block of the S12 core platform A block diagram of the interrupt sub block is shown in Figure 5 1 Figure 5 1 INTV1 Block Diagram HPRIO OPTIONAL INT PRIORITY DECODER VECTOR REQUEST INTERRUPTS RESET FLAGS WRITE DATA BUS HPRIO VECTOR XMASK IMASK QUALIFIED INTERRUPT INPUT REGISTERS INTERRUPTS AND CONTROL REGISTERS HIGHEST PRIORITY I INTERRUPT READ DATA BUS WAKEUP VECTOR ADDRESS INTERRUPT PENDING ...

Page 158: ...reset vectors 0xFFFA 0xFFFE reset CMR and COP Determines the appropriate vector and drives it onto the address bus at the appropriate time Signals the CPU that interrupts are pending Provides control registers which allow testing of interrupts Provides additional input signals which prevents requests for servicing I and X interrupts Wakes the system from stop or wait mode when an appropriate inter...

Page 159: ...associated bits are given in the subsections that follow 5 3 1 Module Memory Map 5 3 2 Register Descriptions 5 3 2 1 Interrupt Test Control Register Read See individual bit descriptions Write See individual bit descriptions Table 5 1 INT Memory Map Address Offset Use Access 0x0015 Interrupt Test Control Register ITCR R W 0x0016 Interrupt Test Registers ITEST R W 0x001F Highest Priority Interrupt O...

Page 160: ...l return the state of the interrupt inputs 1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers instead Note Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten 3 0 ADR 3 0 Test Register Select Bits Read anytime Write anytime These bits determine which test register is selected on a read o...

Page 161: ...interrupt requested by a system block such as a peripheral block has reached the INT module There is a test register implemented for every eight interrupts in the overall system All of the test registers share the same address and are individually selected using the value stored in the ADR 3 0 bits of the interrupt test control register ITCR Note When ADR 3 0 have the value of 0x000F only bits 2 0...

Page 162: ...et request crystal monitor reset request and COP watchdog reset request The type of reset exception request must be decoded by the system and the proper request made to the core The INT will then provide the service routine address for the type of reset requested 5 6 Interrupts As shown in the block diagram in Figure 5 1 the INT contains a register block to provide interrupt status and control an ...

Page 163: ... the exception request may not be processed If for any reason the interrupt source is unknown e g an interrupt request becomes inactive after the interrupt has been recognized but prior to the vector request the vector address will default to that of the last valid interrupt that existed during the particular interrupt sequence If the CPU requests an interrupt vector when there has never been a pe...

Page 164: ...Chapter 5 Interrupt INTV1 Block Description 164 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 165: ... the target and host while allowing more flexibility in clock rates This includes a sync signal to show the clock rate and a handshake signal to indicate when an operation is complete The system is backwards compatible with older external interfaces 6 1 1 Features Single wire communication with host development system BDMV4 and BDM2 Enhanced capability for allowing more flexibility in clock rates ...

Page 166: ...DM does not provide controls to conserve power during run mode Normal operation General operation of the BDM is available and operates the same in all normal modes Special single chip mode In special single chip mode background operation is enabled and active out of reset This allows programming a system with blank memory Special peripheral mode BDM is enabled and active immediately out of reset B...

Page 167: ...make certain All MCUs at the time of this writing have followed this pin sharing scheme 6 2 1 BKGD Background Interface Pin Debugging control logic communicates with external devices serially via the single wire background interface pin BKGD During reset this pin is a mode select input which selects between normal and special modes of operation After reset this pin becomes the dedicated serial int...

Page 168: ...essed by host driven communications to the BDM hardware using READ_BD and WRITE_BD commands Detailed descriptions of the registers and associated bits are given in the subsections that follow 6 3 1 Module Memory Map Table 6 1 INT Memory Map Register Address Use Access 0xFF00 Reserved 0xFF01 BDM Status Register BDMSTS R W 0xFF02 0xFF05 Reserved 0xFF06 BDM CCR Holding Register BDMCCR R W 0xFF07 BDM ...

Page 169: ...served R X X X X X X X X W 0xFF03 Reserved R X X X X X X X X W 0xFF04 Reserved R X X X X X X X X W 0xFF05 Reserved R X X X X X X X X W 0xFF06 BDMCCR R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 W 0xFF07 BDMINR R 0 REG14 REG13 REG12 REG11 0 0 0 W 0xFF08 Reserved R 0 0 0 0 0 0 0 0 W 0xFF09 Reserved R 0 0 0 0 0 0 0 0 W 0xFF0A Reserved R X X X X X X X X W 0xFF0B Reserved R X X X X X X X X W Unimplemented...

Page 170: ...nly be set via a BDM hardware command if the BDM firmware commands are needed This does not apply in special single chip mode 0xFF01 7 6 5 4 3 2 1 0 R ENBDM BDMACT ENTAG SDV TRACE CLKSW UNSEC 0 W Reset Special single chip mode Special peripheral mode All other modes 1 1 0 0 0 1 ENBDM is read as 1 by a debugging environment in Special single chip mode when the device is not secured or secured but f...

Page 171: ...M active 5 ENTAG Tagging Enable This bit indicates whether instruction tagging in enabled or disabled It is set when the TAGGO command is executed and cleared when BDM is entered The serial system is disabled and the tag function enabled 16 cycles after this bit is written BDM cannot process serial commands while tagging is active 0 Tagging not enabled or BDM active 1 Tagging enabled 4 SDV Shift D...

Page 172: ...K to be at the new rate for the write command which changes it 1 UNSEC Unsecure This bit is only writable in special single chip mode from the BDM secure firmware and always gets reset to zero It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map along with the standard BDM firmware lookup table The secure BDM firmware l...

Page 173: ...BDM firmware mode The BDM CCR holding register can be written to modify the CCR value 6 3 2 3 BDM Internal Register Position Register BDMINR Read All modes Write Never 0xFF06 7 6 5 4 3 2 1 0 R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 W Reset 0 0 0 0 0 0 0 0 Figure 6 4 BDM CCR Holding Register BDMCCR 0xFF07 7 6 5 4 3 2 1 0 R 0 REG14 REG13 REG12 REG11 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Re...

Page 174: ...being the case the UNSEC bit will get set The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and all BDM commands are allowed If the EEPROM or FLASH do not verify as erased the BDM firmware sets the ENBDM bit without asserting UNSEC and the firmware enters a loop This causes the BDM hardware commands to become enabled but does not enable...

Page 175: ...e commands are used to read and write target system memory locations and to enter active background debug mode Target system memory includes all memory that is accessible by the CPU such as on chip RAM EEPROM FLASH EEPROM I O and control registers and all external memory Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for executi...

Page 176: ...standard BDM Table 6 5 Hardware Commands Command Opcode hex Data Description BACKGROUND 90 None Enter background mode if firmware is enabled If enabled an ACK will be issued when the part enters active background mode ACK_ENABLE D5 None Enable handshake Issues an ACK pulse after the command is executed ACK_DISABLE D6 None Disable handshake This command does not issue an ACK pulse READ_BD_BYTE E4 1...

Page 177: ...ram counter READ_D 64 16 bit data out Read D accumulator READ_X 65 16 bit data out Read X index register READ_Y 66 16 bit data out Read Y index register READ_SP 67 16 bit data out Read stack pointer WRITE_NEXT 42 16 bit data in Increment X by 2 X X 2 then write word to location pointed to by X WRITE_PC 43 16 bit data in Write program counter WRITE_D 44 16 bit data in Write D accumulator WRITE_X 45...

Page 178: ...egister ready to be shifted out NOTE This timing has increased from previous BDM modules due to the new capability in which the BDM serial interface can potentially run faster than the bus On previous BDM modules this extra time could be hidden within the serial time For firmware write commands the external host must wait 32 bus clock cycles after sending the data to be written before attempting t...

Page 179: ... weak on chip active pull up that is enabled at all times It is assumed that there is an external pull up and that drivers connected to BKGD do not typically drive the high level Because R C rise time could be unacceptably long the target system and host provide brief driven high speedup pulses to drive BKGD to a logic 1 The source of this speedup pulse is the host for transmit cases and the targe...

Page 180: ... Because the host drives the high speedup pulses in these two cases the rising edges look like digitally driven signals Figure 6 7 BDM Host to Target Serial Bit Timing The receive cases are more complicated Figure 6 8 shows the host receiving a logic 1 from the target system Because the host is asynchronous to the target there is up to one clock cycle delay from the host generated falling edge on ...

Page 181: ... host to receive a logic 0 it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge The host samples the bit level about 10 target clock cycles after starting the bit time Figure 6 9 BDM Target to Host Serial Bit Timing Logic 0 HIGH IMPEDANCE EARLIEST START OF NEXT BIT R C RISE 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN PERCEIVED START OF BIT TIM...

Page 182: ... command was a read command or start a new command if the last command was a write command or a control command BACKGROUND GO GO_UNTIL or TRACE1 The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued The end of the BDM command is assumed to be the 16th tick of the last bit This minimum delay assures enough time for the host to perceive the ACK pulse Note a...

Page 183: ...ctrical conflict is when one side is driving low and the other side is issuing a speedup pulse high Other highs are pulled rather than driven However at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well The ACK handshake protocol does not support nested ACK pulses If a BDM command is not acknowledge by an ACK pulse the host needs t...

Page 184: ...this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse In this case the target may not perceive the abort pulse The worst case is when the pending command is a read command i e READ_BYTE If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued while the target expects the host to retriev...

Page 185: ...rmation is being provided so that the MCU integrator will be aware that such a conflict could eventually occur The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol It also allows for new POD devices that support the h...

Page 186: ...et supports the hardware handshake protocol If the target does not support the hardware handshake protocol the ACK pulse is not issued In this case the ACK_ENABLE command is ignored by the target because it is not recognized as a valid command The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode The ACK pulse related to this command could be aborted us...

Page 187: ...everts to high impedance The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications Typically the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent As soon as the SYNC request is detected by ...

Page 188: ...KGD signal Table 6 7 shows the functions of the two tagging pins The pins operate independently that is the state of one pin does not affect the function of the other The presence of logic level 0 on either pin at the fall of the external clock ECLK performs the indicated function High tagging is allowed in all modes Low tagging is allowed only when low strobe is enabled LSTRB is allowed only in w...

Page 189: ...able for retrieval Any falling edge of the BKGD pin after the time out period is considered to be a new command or a SYNC request Note that whenever a partially issued command or partially retrieved data has occurred the time out in the serial communication is active This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the comma...

Page 190: ...Chapter 6 Background Debug Module BDMV4 Block Description 190 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 191: ... architecture 7 1 1 Features The DBG module in BKP mode includes these distinctive features Full or dual breakpoint mode Compare on address and data full Compare on either of two addresses dual BDM or SWI breakpoint Enter BDM on breakpoint BDM Execute SWI on breakpoint SWI Tagged or forced breakpoint Break just before a specific instruction will begin execution TAG Break on the first instruction b...

Page 192: ...fer address is read Two types of breakpoint or debug triggers Break just before a specific instruction will begin execution tag Break on the first instruction boundary after a match occurs force BDM or SWI breakpoint Enter BDM on breakpoint BDM Execute SWI on breakpoint SWI Nine trigger modes for comparators A and B A A or B A then B A and B where B is data full mode A and not B where B is data fu...

Page 193: ...atch on address and data will cause the system to enter background debug mode BDM or initiate a software interrupt SWI In debug mode there are several sub modes of operation Trigger modes There are many ways to create a logical trigger The trigger can be used to capture bus information either starting from the trigger or ending at the trigger Types of triggers A and B are registers A only A or B A...

Page 194: ...DDRESSES ADDRESS HIGH ADDRESS LOW DATA HIGH DATA LOW ADDRESS HIGH ADDRESS LOW COMPARATOR COMPARATOR READ DATA HIGH READ DATA LOW CLOCKS AND BKP CONTROL CONTROL SIGNALS SIGNALS CONTROL BLOCK BREAKPOINT MODES AND GENERATION OF SWI FORCE BDM AND TAGS EXPANSION ADDRESS ADDRESS WRITE DATA READ DATA READ WRITE CONTROL CONTROL BITS CONTROL SIGNALS RESULTS SIGNALS BKP0H BKP0L BKP0X BKPCT0 BKP1X BKPCT1 BKP...

Page 195: ... into the instruction queue PE3 LSTRB TAGLO TAGLO In expanded wide mode or emulation narrow modes when instruction tagging is on and low strobe is enabled a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue TAG FORCE ADDRESS BUS MATCH_A CONTROL READ DATA BUS READ WRITE STORE MCU IN BDM M U X POINTER REGISTER MATCH_B M U X EVENT ONLY WRITE DA...

Page 196: ...r DBGC1 R W 0x0021 Debug Status and Control Register DBGSC R W 0x0022 Debug Trace Buffer Register High DBGTBH R 0x0023 Debug Trace Buffer Register Low DBGTBL R 0x0024 Debug Count Register DBGCNT R 0x0025 Debug Comparator C Extended Register DBGCCX R W 0x0026 Debug Comparator C Register High DBGCCH R W 0x0027 Debug Comparator C Register Low DBGCCL R W 0x0028 Debug Control Register 2 DBGC2 BKPCT0 R ...

Page 197: ... W 0x0027 DBGCCL 2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0028 DBGC2 BKPCT0 R BKABEN FULL BDM TAGAB BKCEN TAGC RWCEN RWC W 0x0029 DBGC3 BKPCT1 R BKAMBH BKAMBL BKBMBH BKBMBL RWAEN RWA RWBEN RWB W 0x002A DBGCAX BKP0X R PAGSEL EXTCMP W 0x002B DBGCAH BKP0H R Bit 15 14 13 12 11 10 9 Bit 8 W 0x002C DBGCAL BKP0L R Bit 7 6 5 4 3 2 1 Bit 0 W 0x002D DBGCBX BKP1X R PAGSEL EXTCMP W 0x002E DBGCBH BKP1H R Bit 15 14 13 1...

Page 198: ...e enabled 6 ARM Arm Bit The ARM bit controls whether the debugger is comparing and storing data in the trace buffer See Section 7 4 2 4 Arming the DBG Module for more information 0 Debugger unarmed 1 Debugger armed Note This bit cannot be set if the DBGEN bit is not also being set at the same time For example a write of 01 to DBGEN 7 6 will be interpreted as a write of 00 5 TRGSEL Trigger Selectio...

Page 199: ... CAPMOD Capture Mode Field See Table 7 4 for capture mode field definitions In LOOP1 mode the debugger will automatically inhibit redundant entries into capture memory In detail mode the debugger is storing address and data for all cycles except program fetch P and free f cycles In profile mode the debugger is returning the address of the last instruction executed by the CPU on each access of trac...

Page 200: ...igger B Match Flag The BF bit indicates if trigger B match condition was met since arming This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register 0 Trigger B did not match 1 Trigger B match 5 CF Comparator C Match Flag The CF bit indicates if comparator C match condition was met since arming This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to...

Page 201: ...nimplemented or Reserved Figure 7 7 Debug Trace Buffer Register Low DBGTBL Table 7 7 DBGTB Field Descriptions Field Description 15 0 Trace Buffer Data Bits The trace buffer data bits contain the data of the trace buffer This register can be read only as a word read Any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the n...

Page 202: ... CNT 5 0 The TBF bit is cleared when ARM in DBGC1 is written to a 1 5 0 CNT Count Value The CNT bits indicate the number of valid data words stored in the trace buffer Table 7 9 shows the correlation between the CNT bits and the number of valid data words in the trace buffer When the CNT rolls over to 0 the TBF bit will be set and incrementing of CNT will continue if DBG is in end trigger mode The...

Page 203: ...Table 7 11 along with the appropriate PPAGE DPAGE or EPAGE signal from the core Note Comparator C can be used when the DBG module is configured for BKP mode Extended addressing comparisons for comparator C use PAGSEL and will operate differently to the way that comparator A and B operate in BKP mode Table 7 11 PAGSEL Decoding 1 1 See Figure 7 10 PAGSEL Description EXTCMP Comment 00 Normal 64k Not ...

Page 204: ...HCS12 implementations are limited to six PPAGE bits PIX 5 0 Therefore EXTCMP 5 4 00 Figure 7 10 Comparator C Extended Comparison in BKP DBG Mode Module Base 0x0026 Starting address location affected by INITRG register setting 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 7 11 Debug Comparator C Register High D...

Page 205: ...GC2 are available When BKABEN is cleared and DBG is used in DBG mode bits FULL and TAGAB have no meaning FULL BDM TAGAB BKCEN 2 2 These bits can be used in BKP mode and DBG mode when capture mode is not set in LOOP1 to provide a third breakpoint TAGC2 RWCEN2 RWC2 W Reset 0 0 0 0 0 0 0 0 Table 7 14 DBGC2 Field Descriptions Field Description 7 BKABEN Breakpoint Using Comparator A and B Enable This b...

Page 206: ...ause a break on the next instruction boundary force or on a match that will be an executable opcode tagged Non executed opcodes cannot cause a tagged breakpoint 0 On match break at the next instruction boundary force 1 On match break if when the instruction is about to be executed tagged 1 RWCEN Read Write Comparator C Enable Bit The RWCEN bit controls whether read or write comparison is enabled f...

Page 207: ... bytes of the second address breakpoint The functionality is as given in Table 7 17 The x 0 case is for a full address compare When a program page is selected the full address compare will be based on bits for a 20 bit compare The registers used for the compare are DBGCBX 5 0 DBGCBH 5 0 DBGCBL 7 0 where DBGCBX 5 0 corresponds to PPAGE 5 0 or extended address bits 19 14 and CPU address 13 0 When a ...

Page 208: ...used in full mode Table 7 16 Breakpoint Mask Bits for First Address BKAMBH BKAMBL Address Compare DBGCAX DBGCAH DBGCAL x 0 Full address compare Yes 1 1 If PPAGE is selected Yes Yes 0 1 256 byte address range Yes1 Yes No 1 1 16K byte address range Yes1 No No Table 7 17 Breakpoint Mask Bits for Second Address Dual Mode BKBMBH BKBMBL Address Compare DBGCBX DBGCBH DBGCBL x 0 Full address compare Yes 1...

Page 209: ...ll be interpreted as values of 00 and 01 respectively In BKP mode PAGSEL has no meaning and EXTCMP 5 0 are compared to address bits 19 14 if the address is in the FLASH ROM memory space 5 0 EXTCMP Comparator A Extended Compare Bits The EXTCMP bits are used as comparison address bits as shown in Table 7 20 along with the appropriate PPAGE DPAGE or EPAGE signal from the core Table 7 20 Comparator A ...

Page 210: ...Starting address location affected by INITRG register setting 15 14 13 12 11 10 9 8 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 0 0 0 0 0 Figure 7 17 Debug Comparator A Register High DBGCAH Module Base 0x002C Starting address location affected by INITRG register setting 7 6 5 4 3 2 1 0 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 0 0 0 0 0 0 0 0 Figure 7 18 D...

Page 211: ...AGE are not yet implemented so the value in bit 7 will be ignored i e PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01 respectively In BKP mode PAGSEL has no meaning and EXTCMP 5 0 are compared to address bits 19 14 if the address is in the FLASH ROM memory space 5 0 EXTCMP Comparator B Extended Compare Bits The EXTCMP bits are used as comparison address bits as shown in Table...

Page 212: ... mode and full breakpoint mode Within each of these modes forced or tagged breakpoint types can be used Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before the tagged instruction executes The action taken upon a successful match can be to either place the CPU in background debug mode or to initiate a software interrupt T...

Page 213: ...DBGC3 select whether or not the breakpoint is matched exactly is a range breakpoint or is in page space The BKBMBH L bits in DBGC3 select whether the data is matched on the high byte low byte or both bytes RWA and RWAEN bits in DBGC2 select whether the type of bus cycle to match is a read or a write when performing forced breakpoints RWB and RWBEN bits in DBGC2 are not used in full breakpoint mode...

Page 214: ...g comparator C Four additional bits BKCEN TAGC RWCEN and RWC in DBGC2 in conjunction with additional comparator C address registers DBGCCX DBGCCH and DBGCCL allow the user to set up a third breakpoint Using PAGSEL in DBGCCX for expanded memory will work differently than the way paged memory is done using comparator A and B in BKP mode See Section 7 3 2 5 Debug Comparator C Extended Register DBGCCX...

Page 215: ... 1 2 Trigger Selection The TRGSEL bit in DBGC1 is used to determine the triggering condition in DBG mode TRGSEL applies to both trigger A and B except in the event only trigger modes By setting TRGSEL the comparators A and B will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged instruction executes tagged type trigger With the TRGSEL bit cleared a com...

Page 216: ...s met the appropriate flag A or B is set in DBGSC Arming the DBG module clears the A B and C flags in DBGSC In all trigger modes except for the event only modes and DETAIL capture mode change of flow addresses are stored in the trace buffer In the event only modes only the value on the data bus at the trigger event B will be stored In DETAIL capture mode address and data for all cycles except prog...

Page 217: ...Section 7 4 2 7 Storage Memory for more information This trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority TRGSEL and BEGIN will not be ignored and this trigger mode will be the same as A then B 7 4 2 5 6 A and B Full Mode In the A and B trigger mode comparator A compares to the address bus and comparator B compares to the data bus In the A and...

Page 218: ...y if the aligned address is outside the range 7 4 2 5 10 Control Bit Priorities The definitions of some of the control bits are incompatible with each other Table 7 25 and the notes associated with it summarize how these incompatibilities are managed Read write comparisons are not compatible with TRGSEL 1 Therefore RWAEN and RWBEN are ignored Event only trigger modes are always considered a begin ...

Page 219: ...ode only inhibits duplicate source address entries that would typically be stored in most tight looping constructs It will not inhibit repeated entries of destination addresses or vector addresses because repeated entries of these would most likely indicate a bug in the user s code that the DBG module is designed to help find NOTE In certain very tight loops the source address will have already be...

Page 220: ...or event only and detail capture mode the data stored in the trace buffer will be change of flow addresses change of flow addresses are defined as follows Source address of conditional branches long short BRSET and loop constructs taken Destination address of indexed JMP JSR and CALL instruction Destination address of RTI RTS and RTC instructions Vector address of interrupts except for SWI and BDM...

Page 221: ...rrect interpretation of the trace buffer data 7 4 3 Breakpoints There are two ways of getting a breakpoint in DBG mode One is based on the trigger condition of the trigger mode using comparator A and or B and the other is using comparator C External breakpoints generated using the TAGHI and TAGLO external pins are disabled in DBG mode 7 4 3 1 Breakpoint Based on Comparator A and B A breakpoint req...

Page 222: ... are selected disarming the DBG in the SWI interrupt service routine is the recommended way to avoid re triggering a breakpoint 7 5 Resets The DBG module is disabled after reset The DBG module cannot cause a MCU reset 7 6 Interrupts The DBG contains one interrupt source If a breakpoint is requested and BDM in DBGC2 is cleared an SWI interrupt will be generated Table 7 26 Breakpoint Setup BEGIN TRG...

Page 223: ...ng modes that are unique to the HC12 design 8 1 1 Features 8 10 bit resolution 7 µsec 10 bit single conversion time Sample buffer amplifier Programmable sample time Left right justified signed unsigned result data External trigger control Conversion completion interrupt generation Analog input multiplexer for eight analog input channels Analog digital input pin multiplexing 1 to 8 conversion seque...

Page 224: ...n either continues or aborts for low power depending on the logical value of the AWAIT bit Freeze Mode In freeze mode the ATD10B8C will behave according to the logical values of the FRZ1 and FRZ0 bits This is useful for debugging and emulation 8 1 3 Block Diagram Figure 8 1 is a block diagram of the ATD Figure 8 1 ATD10B8C Block Diagram VRL AN0 PAD0 ATD10B8C PORT AD DATA REGISTER ANALOG MUX MODE A...

Page 225: ... general purpose digital I O 8 2 4 AN4 PAD4 This pin serves as the analog input channel 4 It can be configured as general purpose digital I O 8 2 5 AN3 PAD3 This pin serves as the analog input channel 3 It can be configured as general purpose digital I O 8 2 6 AN2 PAD2 This pin serves as the analog input channel 2 It can be configured as general purpose digital I O 8 2 7 AN1 PAD1 This pin serves a...

Page 226: ... 0x0003 ATDCTL3 R 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 W 0x0004 ATDCTL4 R SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 W 0x0005 ATDCTL5 R DJM DSGN SCAN MULT 0 CC CB CA W 0x0006 ATDSTAT0 R SCF 0 ETORF FIFOR 0 CC2 CC1 CC0 W 0x0007 Unimplemented R 0 0 0 0 0 0 0 0 W 0x0008 ATDTEST0 R U U U U U U U U W 0x0009 ATDTEST1 R U U U U U U U SC W 0x000A Unimplemented R 0 0 0 0 0 0 0 0 W 0x000B ATDSTAT1 R CCF7 CCF6 CCF...

Page 227: ... u BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 W 0x0016 ATDDR3H R BIT 9 MSB BIT 7 MSB BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 W 0x0017 ATDDR3L R BIT 1 u BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 W 0x0018 ATDDR4H R BIT 9 MSB BIT 7 MSB BIT 8 BIT 6 BIT 7 BIT 5 BIT 6 BIT 4 BIT 5 BIT 3 BIT 4 BIT 2 BIT 3 BIT 1 BIT 2 BIT 0 W 0x0019 ATDDR4L R BIT 1 u BIT 0 u 0 0 0 0 0 0 0 0 0 0 0 0 W...

Page 228: ...IT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 W 0x0014 ATDDR2H R 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 W 0x0015 ATDDR2L R BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 W 0x0016 ATDDR3H R 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 W 0x0017 ATDDR3L R BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 W...

Page 229: ...the module level 0x001C ATDDR6H R 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 W 0x001D ATDDR6L R BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 W 0x001E ATDDR7H R 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 W 0x001F ATDDR7L R BIT 7 BIT 7 MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 BIT 0 BIT 0 W Address Name Bit 7 ...

Page 230: ... normal modes Write Unimplemented in normal modes 8 3 2 2 Reserved Register ATDCTL1 Read Always read 00 in normal modes Write Unimplemented in normal modes NOTE Writing to this registers when in special modes can alter functionality Module Base 0x0000 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 8 3 Reserved Register ATDCTL0 Module Base 0x0001 7 6 5 4 ...

Page 231: ...D conversion complete flags to a fast clear sequence Any access to a result register will cause the associate CCF flag to clear automatically 5 AWAI ATD Power Down in Wait Mode When entering Wait Mode this bit provides on off control over the ATD10B8C block allowing reduced MCU power Because analog electronic is turned off when powered down the ATD requires a recovery time period after exit from W...

Page 232: ...the SCF flag see Section 8 3 2 7 ATD Status Register 0 ATDSTAT0 else ASCIF reads zero Writes have no effect 0 No ATD interrupt occurred 1 ATD sequence complete interrupt pending Table 8 2 External Trigger Configurations ETRIGLE ETRIGP External Trigger Sensitivity 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level Module Base 0x0003 7 6 5 4 3 2 1 0 R 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 W Re...

Page 233: ...rst result register ATDDDR0 Intended usage of FIFO mode is continuos conversion SCAN 1 or triggered conversion ETRIG 1 Which result registers hold valid data can be tracked using the conversion complete flags Fast flag clear mode may or may not be useful in a particular application to track valid data 0 Conversion results are placed in the corresponding result register up to the selected sequence ...

Page 234: ...e second phase of the sample time in units of ATD conversion clock cycles Note that the ATD conversion clock period is itself a function of the prescaler value bits PRS4 0 The sample time consists of two phases The first phase is two ATD conversion clock cycles long and transfers the sample quickly via the buffer amplifier onto the A D machine s storage node The second phase attaches the external ...

Page 235: ...1111 Divide by 2 Divide by 4 Divide by 6 Divide by 8 Divide by 10 Divide by 12 Divide by 14 Divide by 16 Divide by 18 Divide by 20 Divide by 22 Divide by 24 Divide by 26 Divide by 28 Divide by 30 Divide by 32 Divide by 34 Divide by 36 Divide by 38 Divide by 40 Divide by 42 Divide by 44 Divide by 46 Divide by 48 Divide by 50 Divide by 52 Divide by 54 Divide by 56 Divide by 58 Divide by 60 Divide by...

Page 236: ...rol bits Table 8 11 illustrates the difference between the signed and unsigned left justified output codes for an input signal range between 0 and 5 12 Volts 5 SCAN Continuous Conversion Sequence Mode This bit selects whether conversion sequences are performed continuously or only once 0 Single conversion sequence 1 Continuous conversion sequences scan mode 4 MULT Multi Channel Sample Mode When MU...

Page 237: ...nsigned bits 6 15 10 bit left justified signed bits 6 15 10 bit right justified unsigned bits 0 9 Table 8 11 Left Justified Signed and Unsigned ATD Output Codes Input Signal VRL 0 Volts VRH 5 12 Volts Signed 8 Bit Codes Unsigned 8 Bit Codes Signed 10 Bit Codes Unsigned 10 Bit Codes 5 120 Volts 5 100 5 080 2 580 2 560 2 540 0 020 0 000 7F 7F 7E 01 00 FF 81 80 FF FF FE 81 80 7F 01 00 7FC0 7F00 7E00 ...

Page 238: ...f a conversion sequence If conversion sequences are continuously performed SCAN 1 the flag is set after each one is completed This flag is cleared when one of the following occurs A Write 1 to SCF B Write to ATDCTL5 a new conversion sequence is started C If AFFC 1 and read of a result register 0 Conversion sequence not completed 1 Conversion sequence has completed 5 ETORF External Trigger Overrun ...

Page 239: ...s A Write 1 to FIFOR B Start a new conversion sequence write to ATDCTL5 or external trigger 0 No over run has occurred 1 An over run condition exists 2 0 CC 2 0 Conversion Counter These 3 read only bits are the binary value of the conversion counter The conversion counter points to the result register that will receive the result of the current conversion For example CC2 1 CC1 1 CC0 0 indicates th...

Page 240: ...ed Figure 8 11 ATD Test Register 1 ATDTEST1 Table 8 14 ATDTEST1 Field Descriptions Field Description 0 SC Special Channel Conversion Bit If this bit is set then special channel conversion can be selected using CC CB and CA of ATDCTL5 Table 8 15 lists the coding 0 Special channel conversions disabled 1 Special channel conversions enabled Note Always write remaining bits of ATDTEST1 Bit7 to Bit1 zer...

Page 241: ... complete flag is set at the end of each conversion in a conversion sequence The flags are associated with the conversion position in a sequence and also the result register number Therefore CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0 CCF1 is set when the second conversion in a sequence is complete and the result is availabl...

Page 242: ...e 8 17 ATDDIEN Field Descriptions Field Description 7 0 IEN 7 0 ATD Digital Input Enable on channel x x 7 6 5 4 3 2 1 0 This bit controls the digital input buffer from the analog input pin ANx to PTADx data register 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx Note Setting this bit will enable the corresponding digital input buffer continuously If this bit is set ...

Page 243: ...ond there is signed and unsigned data this selection is made using the DSGN control bit in ATDCTL5 Signed data is stored in 2 s complement format and only exists in left justified format Signed data selected for right justified format is ignored Read Anytime Write Anytime no effect in normal modes Module Base 0x000F 7 6 5 4 3 2 1 0 R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0 W Reset 1 1 1 1 ...

Page 244: ...1D ATDDR6L 0x001F ATDDR7L 7 6 5 4 3 2 1 0 R BIT 1 U BIT 0 U 0 0 0 0 0 0 0 0 0 0 0 0 10 bit data 8 bit data W Reset 0 0 0 0 0 0 0 0 Figure 8 16 Left Justified ATD Conversion Result Register Low Byte ATDDRxL Module Base 0x0010 ATDDR0H 0x0012 ATDDR1H 0x0014 ATDDR2H 0x0016 ATDDR3H 0x0018 ATDDR4H 0x001A ATDDR5H 0x001C ATDDR6H 0x001E ATDDR7H 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 BIT 9 MSB 0 BIT 8 0 ...

Page 245: ... and the analog power consumption The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA 8 4 1 2 Analog Input Multiplexer The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine 8 4 1 3 Sample Buffer Amplifier The sample amplifier is used to buffer the input analog signal so that the storage node can b...

Page 246: ...s Clock cycle plus any skew or delay introduced by the trigger circuitry NOTE The conversion results for the external trigger ATD channel 7 have no meaning while external trigger mode is enabled Once ETRIGE is enabled conversions cannot be started by a write to ATDCTL5 but rather must be triggered externally If the level mode is active and the external trigger both de asserts and re asserts itself...

Page 247: ...ill resume A D conversion But due to the recovery time the result of this conversion should be ignored 2 Wait Mode with AWAI 1 This halts A D conversion Exit from Wait mode will resume A D conversion but due to the recovery time the result of this conversion should be ignored 3 Writing ADPU 0 Note that all ATD registers remain accessible This aborts any A D conversion in progress NOTE The reset va...

Page 248: ...your write ATDCTL5 in the last step Example Leave CC CB CA clear to start on channel AN0 Write MULT 1 to convert channel AN0 to AN3 in a sequence 4 conversion per sequence selected in ATDCTL3 8 5 2 Aborting an A D conversion 8 5 2 1 Step 1 Disable the ATD Interrupt by writing ASCIE 0 in ATDCTL2 This will also abort any ongoing conversion sequence It is important to clear the interrupt enable at th...

Page 249: ... 8 7 Interrupts The interrupt requested by the ATD10B8C is listed in Table 8 20 Refer to MCU specification for related vector address and priority See Section 8 3 2 Register Descriptions for further details Table 8 20 ATD10B8C Interrupt Vectors Interrupt Source CCR Mask Local Enable Sequence complete interrupt I bit ASCIE in ATDCTL2 ...

Page 250: ...Chapter 8 Analog to Digital Converter ATD10B8C Block Description 250 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 251: ...ency lock detector CPU interrupt on entry or exit from locked condition Self clock mode in absence of reference clock System clock generator Clock quality check Clock switch for either oscillator or PLL based system clocks User selectable disabling of clocks during wait mode for reduced power consumption Computer operating properly COP watchdog timer with time out clear window System reset generat...

Page 252: ... is disabled and thus all system and core clocks are stopped The COP and the RTI remain frozen Pseudo stop mode The oscillator continues to run and most of the system and core clocks are stopped If the respective enable bits are set the COP and RTI will continue to run else they remain frozen Self clock mode Self clock mode will be entered if the clock monitor enable bit CME and the self clock mod...

Page 253: ...the XFC pin The filter is a second order low pass filter to eliminate the VCO input ripple The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL Refer to the device overview chapter for calculation of PLL loop filter XFC components If PLL usage is not required the XFC pin must be tied to VDDPLL CRG Registers Clock ...

Page 254: ...on all CRGV4 registers Table 9 1 CRGV4 Memory Map Address Offset Use Access 0x0000 CRG Synthesizer Register SYNR R W 0x0001 CRG Reference Divider Register REFDV R W 0x0002 CRG Test Flags Register CTFLG 1 1 CTFLG is intended for factory test purposes only R W 0x0003 CRG Flags Register CRGFLG R W 0x0004 CRG Interrupt Enable Register CRGINT R W 0x0005 CRG Clock Select Register CLKSEL R W 0x0006 CRG P...

Page 255: ...e Bit 7 6 5 4 3 2 1 Bit 0 0x0000 SYNR R 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 W 0x0001 REFDV R 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 W 0x0002 CTFLG R 0 0 0 0 0 0 0 0 W 0x0003 CRGFLG R RTIF PORF LVRF LOCKIF LOCK TRACK SCMIF SCM W 0x0004 CRGINT R RTIE 0 0 LOCKIE 0 0 SCMIE 0 W 0x0005 CLKSEL R PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI W 0x0006 PLLCTL R CME PLLON AUTO ACQ 0 PRE PCE SCME W 0x0007 RT...

Page 256: ...SCM NOTE If PLL is selected PLLSEL 1 Bus Clock PLLCLK 2 Bus Clock must not exceed the maximum operating system frequency Read anytime Write anytime except if PLLSEL 1 NOTE Write to this register initializes the lock detector bit and the track detector bit 0x000B ARMCOP R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Base 0x0000 7 6 5 4 3 2 1 0 R 0 0 SYN5 SYNR SYN3 SYN2 S...

Page 257: ...nd the track detector bit 9 3 2 3 Reserved Register CTFLG This register is reserved for factory testing of the CRGV4 module and is not available in normal modes Read always reads 0x0000 in normal modes Write unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRGV4 functionality Module Base 0x0001 7 6 5 4 3 2 1 0 R 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDV0 W Re...

Page 258: ...on reset occurs This flag can only be cleared by writing a 1 Writing a 0 has no effect 0 Power on reset has not occurred 1 Power on reset has occurred 5 LVRF Low Voltage Reset Flag If low voltage reset feature is not available see the device overview chapter LVRF always reads 0 LVRF is set to 1 when a low voltage reset occurs This flag can only be cleared by writing a 1 Writing a 0 has no effect 0...

Page 259: ...CCLK available 1 MCU is operating in self clock mode with OSCCLK in an unknown state All clocks are derived from PLLCLK running at its minimum frequency fSCM Module Base 0x0004 7 6 5 4 3 2 1 0 R RTIE 0 0 LOCKIE 0 0 SCMIE 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 9 8 CRG Interrupt Enable Register CRGINT Table 9 3 CRGINT Field Descriptions Field Description 7 RTIE Real Time Interrup...

Page 260: ... reduces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly increased power consumption Note Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro magnetic susceptibility EMS tests 5 SYSWAI System Clocks Stop in Wait Mode Bit Write anytime 0 In wait mode the system clocks continue...

Page 261: ...N AUTO ACQ 0 PRE PCE SCME W Reset 1 1 1 1 0 0 0 1 Unimplemented or Reserved Figure 9 10 CRG PLL Control Register PLLCTL Table 9 5 PLLCTL Field Descriptions Field Description 7 CME Clock Monitor Enable Bit CME enables the clock monitor Write anytime except when SCM 1 0 Clock monitor is disabled 1 Clock monitor is enabled Slow or stopped clocks will cause a clock monitor reset sequence or self clock...

Page 262: ...ning during pseudo stop mode 1 RTI continues running during pseudo stop mode Note If the PRE bit is cleared the RTI dividers will go static while pseudo stop mode is active The RTI dividers will not initialize like in wait mode with RTIWAI bit set 1 PCE COP Enable during Pseudo Stop Bit PCE enables the COP during pseudo stop mode Write anytime 0 COP stops running during pseudo stop mode 1 COP cont...

Page 263: ...12 2x213 2x214 2x215 2x216 0010 3 OFF 3x210 3x211 3x212 3x213 3x214 3x215 3x216 0011 4 OFF 4x210 4x211 4x212 4x213 4x214 4x215 4x216 0100 5 OFF 5x210 5x211 5x212 5x213 5x214 5x215 5x216 0101 6 OFF 6x210 6x211 6x212 6x213 6x214 6x215 6x216 0110 7 OFF 7x210 7x211 7x212 7x213 7x214 7x215 7x216 0111 8 OFF 8x210 8x211 8x212 8x213 8x214 8x215 8x216 1000 9 OFF 9x210 9x211 9x212 9x213 9x214 9x215 9x216 10...

Page 264: ...ime out logic restarts and the user must wait until the next window before writing to ARMCOP Table 9 9 shows the exact duration of this window for the seven available COP rates 0 Normal COP operation 1 Window COP operation 6 RSBCK COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in active BDM mode 1 Stops the COP and RTI counters whenever the part is in active BDM m...

Page 265: ...te only in special modes 9 3 2 11 Reserved Register CTCTL NOTE This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in special test modes can alter the CRG s functionality Read always read 0x0080 except in special modes Write only in special modes Module Base 0x0009 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 ...

Page 266: ...t is set 0x0055 and 0x00AA writes must be done in the last 25 of the selected time out period writing any value in the first 75 of the selected period will cause a COP reset 9 4 Functional Description This section gives detailed informations on the internal operation of the design 9 4 1 Phase Locked Loop PLL The PLL is used to run the MCU from a different time base than the incoming OSCCLK For inc...

Page 267: ...eedback clock with the reference clock Correction pulses are generated based on the phase difference between the two signals The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin based on the width and direction of the correction pulse The filter can make fast or slow corrections depending on its mode as described in the next subsection The value...

Page 268: ...the LOCK bit is set is the PLLCLK clock safe to use as the source for the system and core clocks If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear the PLL has suffered a severe noise hit and the software must take appropriate action depending on the application The following conditions apply when the PLL is in automatic bandwidth control mode AUTO 1 The ...

Page 269: ...cy fSCM The bus clock is used to generate the clock visible at the ECLK pin The core clock signal is the clock for the CPU The core clock is twice the bus clock as shown in Figure 9 18 But note that a CPU cycle corresponds to one bus clock PLL clock mode is selected with PLLSEL bit in the CLKSEL register When selected the PLL output clock drives SYSCLK for the main system including the CPU and per...

Page 270: ...r function is enabled disabled by the CME control bit 9 4 4 Clock Quality Checker The clock monitor performs a coarse check on the incoming clock signal The clock quality checker provides a more accurate check in addition to the clock monitor A clock quality check is triggered by any of the following events Power on reset POR Low voltage reset LVR Wake up from full stop mode exit full stop Clock m...

Page 271: ...y checker continues to check the OSCCLK signal NOTE The clock quality checker enables the PLL and the voltage regulator VREG anytime a clock check has to be performed An ongoing clock quality check could also cause a running PLL fSCM and an active VREG during pseudo stop mode or wait mode 1 A Clock Monitor Reset will always set the SCME bit to logical 1 check window osc ok SCM active Switch to OSC...

Page 272: ...oon as this is done the COP time out period is restarted If the program fails to do this and the COP times out the part will reset Also if any value other than 0x0055 or 0x00AA is written the part is immediately reset Windowed COP operation is enabled by setting WCOP in the COPCTL register In this mode writes to the ARMCOP register to clear the COP timer must occur in the last 25 of the selected t...

Page 273: ...start up time the bus clock and the core clock are derived from the VCO running at minimum operating frequency this mode of operation is called self clock mode This requires CME 1 and SCME 1 If the MCU was clocked by the PLL clock prior to entering self clock mode the PLLSEL bit will be cleared If the external clock signal has stabilized again the CRG will automatically select OSCCLK to be the sys...

Page 274: ...n a low power consumption stand by mode depending on setting of the individual bits in the CLKSEL register All individual wait mode configuration bits can be superposed This provides enhanced granularity in reducing the level of power consumption during wait mode Table 9 10 lists the individual configuration bits and the parts of the MCU that are affected in wait mode After executing the WAI instr...

Page 275: ...t Wait w CMRESET Exit Wait w ext RESET Exit Wait Mode Enter SCM Exit Wait Mode Core req s Wait Mode CWAI or SYSWAI 1 SYSWAI 1 Clear PLLSEL Disable PLL Disable core clocks Disable system clocks CME 1 INT CM fail SCME 1 SCMIE 1 Continue w normal OP no no no no no no no yes yes yes yes yes no yes yes yes Wait Mode left due to external reset Generate SCM Interrupt Wakeup from Wait SCM 1 Enter SCM no y...

Page 276: ... to external reset but another reset vector is fetched after completion of the reset sequence If the SCME bit is asserted the CRG generates a SCM interrupt if enabled SCMIE 1 After generating the interrupt the CRG enters self clock mode and starts the clock quality checker see Section 9 4 4 Clock Quality Checker Then the MCU continues with normal operation If the SCM interrupt is blocked by SCMIE ...

Page 277: ...d in Wait Mode MCU remains in Wait Mode Some time later either a wakeup interrupt occurs no SCM interrupt Exit Wait Mode using OSCCLK as system clock SYSCLK Continue normal operation or an External Reset is applied Exit Wait Mode using OSCCLK as system clock Start reset sequence Scenario 2 OSCCLK does not recover prior to exiting Wait Mode MCU remains in Wait Mode VREG enabled PLL enabled SCM acti...

Page 278: ...ode the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit Then the CRG disables the PLL disables the core clock and finally disables the remaining system clocks As soon as all clocks are switched off stop mode is active If pseudo stop mode PSTP 1 is entered from self clock mode the CRG will continue to check the clock quality until clock check is successful The PLL an...

Page 279: ... restart the MCU from pseudo stop mode External reset Clock monitor fail Wake up interrupt Exit Stop w CMRESET Exit Stop Mode Enter SCM Exit Stop Mode Core req s Stop Mode Clear PLLSEL Disable PLL CME 1 INT CM fail SCME 1 SCMIE 1 Continue w normal OP no no no no yes yes yes yes yes Generate SCM Interrupt Wakeup from Stop Enter Stop Mode Exit Stop w ext RESET Wait Mode left due to external Clock OK...

Page 280: ...RESET is the same compared to external reset but another reset vector is fetched after completion of the reset sequence If the SCME bit is asserted the CRG generates a SCM interrupt if enabled SCMIE 1 After generating the interrupt the CRG enters self clock mode and starts the clock quality checker see Section 9 4 4 Clock Quality Checker Then the MCU continues with normal operation If the SCM inte...

Page 281: ...de Some time later either a wakeup interrupt occurs no SCM interrupt Exit Pseudo Stop Mode using OSCCLK as system clock SYSCLK Continue normal operation or an External Reset is applied Exit Pseudo Stop Mode using OSCCLK as system clock Start reset sequence Scenario 2 OSCCLK does not recover prior to exiting Pseudo Stop Mode MCU remains in Pseudo Stop Mode VREG enabled PLL enabled SCM activated Sta...

Page 282: ...failing the CRG will switch to self clock mode or generate a clock monitor reset CMRESET depending on the setting of the SCME bit Because the PLL has been powered down during stop mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode The software must manually set the PLLSEL bit again in order to switch system and core clocks to the PLLCLK NOTE In full stop mode the clo...

Page 283: ...mber of 128 SYSCLK cycles might be increased by n 3 to 6 additional SYSCLK cycles depending on the internal synchronization latency After 128 n SYSCLK cycles the RESET pin is released The reset generator of the CRGV4 waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source Table 9 14 shows which vector will be fetched NOTE External circuitry connecte...

Page 284: ...enters self clock mode and starts its internal reset sequence In parallel the clock quality check starts As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and leaves self clock mode Because the clock quality checker is running in parallel to the reset generator the CRG may leave self clock mode while completing the internal reset sequence When the reset s...

Page 285: ...rts power on reset or low voltage reset or both As soon as a power on reset or low voltage reset is triggered the CRG performs a quality check on the incoming clock signal As soon as clock quality check indicates a valid oscillator clock signal the reset sequence starts using the oscillator clock If after 50 check windows the clock quality check indicated a non valid oscillator clock the reset seq...

Page 286: ... locally disabled by setting the LOCKIE bit to 0 The PLL Lock interrupt flag LOCKIF is set to1 when the LOCK condition has changed and is cleared to 0 by writing a 1 to the LOCKIF bit 9 6 3 Self Clock Mode Interrupt The CRGV4 generates a self clock mode interrupt when the SCM condition of the system has changed either entered or exited self clock mode SCM conditions can only change if the self clo...

Page 287: ...th the terms and concepts contained within this document Though not exclusively intended for automotive applications CAN protocol is designed to meet the specific requirements of a vehicle serial data bus real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidth MSCAN uses an advanced buffer arrangement resulting in predictable real time ...

Page 288: ...s Programmable wakeup functionality with integrated low pass filter Programmable loopback mode supports self test operation Programmable listen only mode for monitoring of CAN bus Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states warning error passive bus off Programmable MSCAN clock source either bus clock or oscillator clock Internal timer for time ...

Page 289: ... RXCAN is the MSCAN receiver input pin 10 2 2 TXCAN CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin The TXCAN output pin represents the logic level on the CAN bus 0 Dominant state 1 Recessive state 10 2 3 CAN System A typical CAN system with MSCAN is shown in Figure 10 2 Each CAN station is connected physically to the CAN bus lines through a transceiver device The transceiver ...

Page 290: ...MSCAN memory map The register address results from the addition of base address and address offset The base address is determined at the MCU level and can be found in the MCU memory map description The address offset is defined at the module level The MSCAN occupies 64 bytes in the memory space The base address of the MSCAN module is determined at the MCU level when the MCU is defined The register...

Page 291: ... RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W 0x0005 CANRIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0006 CANTFLG R 0 0 0 0 0 TXE2 TXE1 TXE0 W 0x0007 CANTIER R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W 0x0008 CANTARQ R 0 0 0 0 0 ABTRQ2 ABTRQ1 ABTRQ0 W 0x0009 CANTAAK R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 W 0x000A CANTBSEL R 0 0 0 0 0 TX2 TX1 TX0 W 0x000B CANIDAC R 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0...

Page 292: ... CANCTL0 register provides various control bits of the MSCAN module as described below 0x0010 0x0013 CANIDAR0 3 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x0014 0x0017 CANIDMRx R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0018 0x001B CANIDAR4 7 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x001C 0x001F CANIDMR4 7 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0020 0x002F CANRXFG R See Section 10 3 3 Programmer s Model of Messag...

Page 293: ...ng or idle2 1 MSCAN is receiving a message including when arbitration is lost 2 5 CSWAI 3 CAN Stops in Wait Mode Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode 4 SYNCH Synchronized Status This read only flag ind...

Page 294: ...AK 1 The values of the error counters are not affected by initialization mode When this bit is cleared by the CPU the MSCAN restarts and then tries to synchronize to the CAN bus If the MSCAN is not in bus off state it synchronizes after 11 consecutive recessive bits on the CAN bus if the MSCAN is in bus off state it continues to wait for 128 occurrences of 11 consecutive recessive bits Writing to ...

Page 295: ...iver internally The RXCAN input pin is ignored and the TXCAN output goes to the recessive state logic 1 The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node In this state the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message Both transmit ...

Page 296: ...g The MSCAN operates normally 1 Sleep mode active The MSCAN has entered sleep mode 0 INITAK Initialization Mode Acknowledge This flag indicates whether the MSCAN module is in initialization mode see Section 10 4 5 5 MSCAN Initialization Mode It is used as a handshake flag for the INITRQ initialization mode request Initialization mode is active when INITRQ 1 and INITAK 1 The registers CANCTL1 CANBT...

Page 297: ...d Descriptions Field Description 7 6 SJW 1 0 Synchronization Jump Width The synchronization jump width defines the maximum number of time quanta Tq clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus see Table 10 4 5 0 BRP 5 0 Baud Rate Prescaler These bits determine the time quanta Tq clock which is used to build up the bit timing see ...

Page 298: ...ositioned at the sample point If SAMP 1 the resulting bit value is determined by using majority rule on the three total samples For higher bit rates it is recommended that only one sample is taken per bit time SAMP 0 1 In this case PHASE_SEG1 must be at least 2 time quanta Tq 6 4 TSEG2 2 0 Time Segment 2 Time segments within the bit time fix the number of clock cycles per bit time and the location...

Page 299: ...nd INITAK 1 This register is writable again as soon as the initialization mode is exited INITRQ 0 and INITAK 0 Read Anytime Write Anytime when out of initialization mode except RSTAT 1 0 and TSTAT 1 0 flags which are read only write of 1 clears flag write of 0 is ignored Table 10 8 Time Segment 1 Values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycle 1 1 This setting is not val...

Page 300: ...e bits RSTAT1 RSTAT0 is 00 RxOK 0 receive error counter 96 01 RxWRN 96 receive error counter 127 10 RxERR 127 receive error counter 11 Bus off 1 transmit error counter 255 1 Redundant Information for the most critical CAN bus status which is bus off This only occurs if the Tx error counter exceeds a number of 255 errors Bus off affects the receiver state As soon as the transmitter leaves its bus o...

Page 301: ... the sensitivity level in which receiver state changes are causing CSCIF interrupts Independent of the chosen sensitivity level the RSTAT flags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending 00 Do not generate any CSCIF interrupt caused by receiver state changes 01 Generate CSCIF interrupt only if the receiver enters or leaves bus off state Dis...

Page 302: ...ceiver Full Interrupt Enable 0 No interrupt request is generated from this event 1 A receive buffer full successful message reception event causes a receiver interrupt request 1 WUPIE and WUPE see Section 10 3 2 1 MSCAN Control Register 0 CANCTL0 must both be enabled if the recovery mechanism from stop or wait is required 2 Bus off state is defined by the CAN standard see Bosch CAN 2 0A B protocol...

Page 303: ...er Message Abort Request Register CANTARQ If not masked a transmit interrupt is pending while this flag is set Clearing a TXEx flag also clears the corresponding ABTAKx see Section 10 3 2 10 MSCAN Transmitter Message Abort Acknowledge Register CANTAAK When a TXEx flag is set the corresponding ABTRQx bit is cleared see Section 10 3 2 9 MSCAN Transmitter Message Abort Request Register CANTARQ When l...

Page 304: ... 0 0 0 Unimplemented Figure 10 12 MSCAN Transmitter Message Abort Request Register CANTARQ Table 10 13 CANTARQ Register Field Descriptions Field Description 2 0 ABTRQ 2 0 Abort Request The CPU sets the ABTRQx bit to request that a scheduled message buffer TXEx 0 be aborted The MSCAN grants the request if the message has not already started transmission or if the transmission is not successful lost...

Page 305: ... ABTAKx flags Module Base 0x0009 7 6 5 4 3 2 1 0 R 0 0 0 0 0 ABTAK2 ABTAK1 ABTAK0 W Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 10 13 MSCAN Transmitter Message Abort Acknowledge Register CANTAAK Table 10 14 CANTAAK Register Field Descriptions Field Description 2 0 ABTAK 2 0 Abort Acknowledge This flag acknowledges that a message was aborted due to a pending abort request from the CPU After a partic...

Page 306: ...G because the lowest numbered bit set to 1 is at bit position 1 Reading back this value out of CANTBSEL results in 0b0000_0010 because only the lowest numbered bit position set to 1 is presented This mechanism eases the application software the selection of the next available Tx buffer LDD CANTFLG value read is 0b0000_0110 STD CANTBSEL value written is 0b0000_0110 LDD CANTBSEL value read is 0b0000...

Page 307: ...efine the identifier acceptance filter organization see Section 10 4 3 Identifier Acceptance Filter Table 10 17 summarizes the different settings In filter closed mode no message is accepted such that the foreground buffer is never reloaded 2 0 IDHIT 2 0 Identifier Acceptance Hit Indicator The MSCAN sets these flags to indicate an identifier acceptance hit see Section 10 4 3 Identifier Acceptance ...

Page 308: ...n normal system operation modes Write Unimplemented in normal system operation modes NOTE Writing to this register when in special modes can alter the MSCAN functionality 10 3 2 14 MSCAN Receive Error Counter CANRXERR This register reflects the status of the MSCAN receive error counter Read Only when in sleep mode SLPRQ 1 and SLPAK 1 or initialization mode INITRQ 1 and INITAK 1 Write Unimplemented...

Page 309: ... CANTXERR This register reflects the status of the MSCAN transmit error counter Read Only when in sleep mode SLPRQ 1 and SLPAK 1 or initialization mode INITRQ 1 and INITAK 1 Write Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value For MCUs with dual CPUs this may result in a CPU fault condition Writing to this regis...

Page 310: ...d For standard identifiers only the first two CANIDAR0 1 CANIDMR0 1 are applied Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 Module Base 0x0010 CANIDAR0 0x0011 CANIDAR1 0x0012 CANIDAR2 0x0013 CANIDAR3 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AC7 AC...

Page 311: ...set 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 0 0 0 0 0 0 0 0 Figure 10 20 MSCAN Identifier Acceptance Registers Second Bank CANIDAR4 CANIDAR7 Table 10 20 CANIDAR4 CANIDAR7 Register Field Descriptions Field Description 7 0 AC 7 0 Acceptance Code Bits AC 7 0 comprise a user defined sequence of ...

Page 312: ...DMR2 0x0017 CANIDMR3 7 6 5 4 3 2 1 0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 0 0 0 0 0 0 0 0 Figure 10 21 MSCAN Identifier Mask Registers First Bank CANIDMR0 CANIDMR3 Table 10 ...

Page 313: ...M3 AM2 AM1 AM0 W Reset 0 0 0 0 0 0 0 0 Figure 10 22 MSCAN Identifier Mask Registers Second Bank CANIDMR4 CANIDMR7 Table 10 22 CANIDMR4 CANIDMR7 Register Field Descriptions Field Description 7 0 AM 7 0 Acceptance Mask Bits If a particular bit in this register is cleared this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a ma...

Page 314: ...tten by the MSCAN The CPU can only read these registers Figure 10 23 shows the common 13 byte data structure of receive and transmit buffers for extended identifiers The mapping of standard identifiers into the IDR registers is shown in Figure 10 24 All bits of the receive and transmit buffers are x out of reset because of RAM based implementation1 All reserved or unused bits of the receive and tr...

Page 315: ... 0x00X0 IDR0 R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 W 0x00X1 IDR1 R ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 W 0x00X2 IDR2 R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W 0x00X3 IDR3 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W 0x00X4 DSR0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X5 DSR1 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X6 DSR2 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X7 DSR3 R DB7 DB6 DB5 DB4 DB3 DB2 DB...

Page 316: ...consist of a total of 13 bits ID 10 0 RTR and IDE bits 10 3 3 1 1 IDR0 IDR3 for Extended Identifier Mapping Register Name Bit 7 6 5 4 3 2 1 Bit 0 IDR0 0x00X0 R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 W IDR1 0x00X1 R ID2 ID1 ID0 RTR IDE 0 W IDR2 0x00X2 R W IDR3 0x00X3 R W Unused always read x Figure 10 24 Receive Transmit Message Buffer Standard Identifier Mapping Module Base 0x00X1 7 6 5 4 3 2 1 0 R ID28...

Page 317: ...identifier format is applied in this buffer In the case of a receive buffer the flag is set as received and indicates to the CPU how to process the buffer identifier registers In the case of a transmit buffer the flag indicates to the MSCAN what type of identifier to send 0 Standard format 11 bit 1 Extended format 29 bit 2 0 ID 17 15 Extended Format Identifier The identifiers consist of 29 bits ID...

Page 318: ...TR Remote Transmission Request This flag reflects the status of the remote transmission request bit in the CAN frame In the case of a receive buffer it indicates the status of the received frame and supports the transmission of an answering frame in software In the case of a transmit buffer this flag defines the setting of the RTR bit to be sent 0 Data frame 1 Remote frame Module Base 0x00X0 7 6 5...

Page 319: ...te Transmission Request This flag reflects the status of the Remote Transmission Request bit in the CAN frame In the case of a receive buffer it indicates the status of the received frame and supports the transmission of an answering frame in software In the case of a transmit buffer this flag defines the setting of the RTR bit to be sent 0 Data frame 1 Remote frame 3 IDE ID Extended This flag ind...

Page 320: ... by the data length code in the corresponding DLR register Module Base 0x00X3 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always read x Figure 10 32 Identifier Register 3 Standard Mapping Module Base 0x0004 DSR0 0x0005 DSR1 0x0006 DSR2 0x0007 DSR3 0x0008 DSR4 0x0009 DSR5 0x000A DSR6 0x000B DSR7 7 6 5 4 3 2 1 0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W Reset x x x x x x x x Figure 10 33 Data Segment...

Page 321: ...frame is sent The transmission buffer with the lowest local priority field wins the prioritization Module Base 0x00XB 7 6 5 4 3 2 1 0 R DLC3 DLC2 DLC1 DLC0 W Reset x x x x x x x x Unused always read x Figure 10 34 Data Length Register DLR Extended Identifier Mapping Table 10 31 DLR Register Field Descriptions Field Description 3 0 DLC 3 0 Data Length Code Bits The data length code contains the num...

Page 322: ...to the respective registers in the active transmit or receive buffer right after the EOF of a valid message on the CAN bus see Section 10 3 2 1 MSCAN Control Register 0 CANCTL0 In case of a transmission the CPU can only read the time stamp after the respective transmit buffer has been flagged empty The timer value which is used for stamping is taken from a free running internal CAN bit clock A tim...

Page 323: ...10 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit buffer is selected in CANTBSEL see Section 10 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Write Unimplemented 10 4 Functional Description 10 4 1 General This section provides a complete functional description of the MSCAN It describes each of the features and modes listed in the introduction ...

Page 324: ... 38 User Model for Message Buffer Organization MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications MSCAN Rx0 Rx1 CAN Receive Transmit Engine CPU12 Memory Mapped I O CPU bus MSCAN Tx2 TXE2 PRIO Receiver Transmitter RxBG TxBG Tx0 TXE0 PRIO TxBG Tx1 PRIO TXE1 TxFG CPU bus Rx2 Rx3 Rx4 RXF RxFG ...

Page 325: ...s The second requirement calls for some sort of internal prioritization which the MSCAN implements with the local priority concept described in Section 10 4 2 2 Transmit Structures 10 4 2 2 Transmit Structures The MSCAN triple transmit buffer scheme optimizes real time performance by allowing multiple messages to be set up in advance The three buffers are arranged as shown in Figure 10 38 All thre...

Page 326: ...errupt The transmit interrupt handler software can determine from the setting of the ABTAK flag whether the message was aborted ABTAK 1 or sent ABTAK 0 10 4 2 3 Receive Structures The received messages are stored in a five stage input FIFO The five message buffers are alternately mapped into a single memory area see Figure 10 38 The background receive buffer RxBG is exclusively associated with the...

Page 327: ...ance Control Register CANIDAC define the acceptable patterns of the standard or extended identifier ID 10 0 or ID 28 0 Any of these bits can be marked don t care in the MSCAN identifier mask registers see Section 10 3 2 17 MSCAN Identifier Mask Registers CANIDMR0 CANIDMR7 A filter hit is indicated to the application software by a set receive buffer full flag RXF 1 and three bits in the CANIDAC reg...

Page 328: ...plements eight independent filters for the first 8 bits of a CAN 2 0A B compliant standard identifier or a CAN 2 0B compliant extended identifier Figure 10 41 shows how the first 32 bit filter bank CANIDAR0 CANIDAR3 CANIDMR0 CANIDMR3 produces filter 0 to 3 hits Similarly the second filter bank CANIDAR4 CANIDAR7 CANIDMR4 CANIDMR7 produces filter 4 to 7 hits Closed filter No CAN message is copied in...

Page 329: ... Acceptance Filters ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CANIDAR0 AM7 AM0 CANIDMR0 AC7 AC0 CANIDAR1 AM7 AM0 CANIDMR1 ID Accepted Filter 0 Hit AC7 AC0 CANIDAR2 AM7 AM0 CANIDMR2 AC7 AC0 CANIDAR3 AM7 AM0 CANIDMR3 ID Accepted Filter 1 Hit CAN 2 0B Extended Identifier CAN 2 0A B Standard Identifier ...

Page 330: ...s CAN 2 0B Extended Identifier CAN 2 0A B Standard Identifier AC7 AC0 CIDAR3 AM7 AM0 CIDMR3 ID Accepted Filter 3 Hit AC7 AC0 CIDAR2 AM7 AM0 CIDMR2 ID Accepted Filter 2 Hit AC7 AC0 CIDAR1 AM7 AM0 CIDMR1 ID Accepted Filter 1 Hit ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CIDAR0 AM7 AM0 CIDMR0 ID Accepted Filter 0 Hit ...

Page 331: ...tifier acceptance registers CANIDAR0 CANIDAR7 MSCAN identifier mask registers CANIDMR0 CANIDMR7 The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode see Section 10 4 5 6 MSCAN Power Down Mode and Section 10 4 5 5 MSCAN Initialization Mode The MSCAN enable bit CANE is writable only once in normal system operation modes which pr...

Page 332: ...nto three segments as described in the Bosch CAN specification see Figure 10 43 SYNC_SEG This segment has a fixed length of one time quantum Signal edges are expected to happen within this section Time Segment 1 This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta Time Segment 2 This segment ...

Page 333: ...s of Operation 10 4 4 1 Normal Modes The MSCAN module behaves as described within this specification in all normal system operation modes 10 4 4 2 Special Modes The MSCAN module behaves as described within this specification in all special system operation modes Table 10 33 Time Segment Syntax Syntax Description SYNC_SEG System expects transitions to occur on the CAN bus during this period Transmi...

Page 334: ...hough the CAN bus may remain in recessive state externally 10 4 4 5 Security Modes The MSCAN module has no security features 10 4 5 Low Power Options If the MSCAN is disabled CANE 0 the MSCAN clocks are stopped for power saving If the MSCAN is enabled CANE 1 the MSCAN has two additional modes with reduced power consumption compared to normal mode sleep and power down mode In sleep mode power consu...

Page 335: ...erate in any of the low power modes depending on the values of the SLPRQ SLPAK and CSWAI bits as seen in Table 10 35 10 4 5 3 Operation in Stop Mode The STOP instruction puts the MCU in a low power consumption stand by mode In stop mode the MSCAN is set in power down mode regardless of the value of the SLPRQ SLPAK and CSWAI bits Table 10 35 10 4 5 4 MSCAN Sleep Mode The CPU can request the MSCAN t...

Page 336: ...10 44 The application software must use SLPAK as a handshake indication for the request SLPRQ to go into sleep mode When in sleep mode SLPRQ 1 and SLPAK 1 the MSCAN stops its internal clocks However clocks that allow register accesses from the CPU side continue to run If the MSCAN is in bus off state it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks T...

Page 337: ... a CAN frame this frame is not received The receive message buffers RxFG and RxBG contain messages if they were received before sleep mode was entered All pending actions will be executed upon wake up copying of RxBG into RxFG message aborts and message transmissions If the MSCAN remains in bus off state after sleep mode was exited it continues counting the 128 occurrences of 11 consecutive recess...

Page 338: ...TFLG CANTIER CANTARQ CANTAAK and CANTBSEL registers to their default values In addition the MSCAN enables the configuration of the CANBTR0 CANBTR1 bit timing registers CANIDAC and the CANIDAR CANIDMR message filters See Section 10 3 2 1 MSCAN Control Register 0 CANCTL0 for a detailed description of the initialization mode Figure 10 46 Initialization Request Acknowledge Cycle Due to independent clo...

Page 339: ... accessed If the MSCAN was not in sleep mode before power down mode became active the module performs an internal recovery cycle after powering up This causes some fixed delay before the module enters normal mode again 10 4 5 7 Programmable Wake Up Function The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected see control bit WUPE in Section 10 3 2 1 MSCAN Contro...

Page 340: ...s soon as the next message is shifted to the foreground buffer 10 4 7 4 Wake Up Interrupt A wake up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode WUPE see Section 10 3 2 1 MSCAN Control Register 0 CANCTL0 must be enabled 10 4 7 5 Error Interrupt An error interrupt is generated if an overrun of the receiver FIFO error warning or bus off condition occurrs S...

Page 341: ... instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine 10 4 7 7 Recovery from Stop or Wait The MSCAN can recover from stop or wait via the wake up interrupt This interrupt can only occur if the MSCAN was in sleep mode SLPRQ 1 and SLPAK 1 before entering power down mode the wake up option is enabled WUPE 1 and the wake up in...

Page 342: ...Chapter 10 Freescale s Scalable Controller Area Network S12MSCANV2 342 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 343: ...s an external damping resistor is not required Normal and low amplitude mode for further reduction of power and emission An external biasing resistor is not required The Pierce OSC option provides the following features Wider high frequency operation range No DC voltage applied across the crystal Full rail to rail 2 5 V nominal swing oscillation with low EM susceptibility Fast start up Common feat...

Page 344: ...ut of the crystal oscillator amplifier All the MCU internal system clocks are derived from the EXTAL input frequency In full stop mode PSTP 0 the EXTAL pin is pulled down by an internal resistor of typical 200 kΩ NOTE Freescale Semiconductor recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier The Crystal circuit is changed from sta...

Page 345: ...Pierce oscillator external clock circuitry is used The XCLKS signal is sampled during reset with the rising edge of RESET Table 11 1 lists the state coding of the sampled XCLKS signal Refer to the device overview chapter for polarity of the XCLKS pin Table 11 1 Clock Selection Based on XCLKS XCLKS Description 0 Colpitts oscillator selected 1 Pierce oscillator external clock selected MCU EXTAL XTAL...

Page 346: ...urce under the control of a peak detector which will measure the amplitude of the AC signal appearing on EXTAL node in order to implement an amplitude limitation control ALC loop The ALC loop is in charge of reducing the quiescent current in the transconductor as a result of an increase in the oscillation amplitude The oscillation amplitude can be limited to two values The normal amplitude which i...

Page 347: ... rates from 0 to 100 The PWM outputs can be programmed as left aligned outputs or center aligned outputs 12 1 1 Features Six independent PWM channels with programmable period and duty cycle Dedicated counter for each PWM channel Programmable PWM enable disable for each channel Software selection of PWM duty pulse polarity for each channel Period and duty cycle are double buffered Change takes effe...

Page 348: ...5 and as an input for the emergency shutdown feature 12 2 2 PWM4 Pulse Width Modulator Channel 4 Pin This pin serves as waveform output of PWM channel 4 12 2 3 PWM3 Pulse Width Modulator Channel 3 Pin This pin serves as waveform output of PWM channel 3 Period and Duty Counter Channel 5 Bus Clock Clock Select PWM Clock Period and Duty Counter Channel 4 Period and Duty Counter Channel 3 Period and D...

Page 349: ...s maps and register diagrams Notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions 12 3 1 Module Memory Map The following paragraphs describe the content of the registers in the PWM8B6CV1 module The base address of the PWM8B6CV1 module is determined at the MCU level when the MCU is defined The register decode m...

Page 350: ...only R W 0x000B PWM Scale B Counter Register PWMSCNTB 4 4 PWMSCNTB is intended for factory test purposes only R W 0x000C PWM Channel 0 Counter Register PWMCNT0 R W 0x000D PWM Channel 1 Counter Register PWMCNT1 R W 0x000E PWM Channel 2 Counter Register PWMCNT2 R W 0x000F PWM Channel 3 Counter Register PWMCNT3 R W 0x0010 PWM Channel 4 Counter Register PWMCNT4 R W 0x0011 PWM Channel 5 Counter Registe...

Page 351: ...LK3 PCLK2 PCLK1 PCLK0 W 0x0003 PWMPRCLK R 0 PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0 W 0x0004 PWMCAE R 0 0 CAE5 CAE4 CAE2 CAE2 CAE1 CAE0 W 0x0005 PWMCTL R 0 CON45 CON23 CON01 PSWAI PFRZ 0 0 W 0x0006 PWMTST R 0 0 0 0 0 0 0 0 W 0x0007 PWMPRSC R 0 0 0 0 0 0 0 0 W 0x0008 PWMSCLA R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0009 PWMSCLB R Bit 7 6 5 4 3 2 1 Bit 0 W 0x000A PWMSCNTA R 0 0 0 0 0 0 0 0 W 0x000B PWMSCNTB R 0 ...

Page 352: ...PWMPER2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0015 PWMPER3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0016 PWMPER4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0017 PWMPER5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0018 PWMDTY0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0019 PWMPER1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001A PWMPER2 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001B PWMPER3 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001C PWMPER4 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001D PWMPER5 R Bit...

Page 353: ...time Write anytime Module Base 0x0000 7 6 5 4 3 2 1 0 R 0 0 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 12 3 PWM Enable Register PWME Table 12 2 PWME Field Descriptions Field Description 5 PWME5 Pulse Width Channel 5 Enable 0 Pulse width channel 5 is disabled 1 Pulse width channel 5 is enabled The pulse modulated signal becomes available at PWM outp...

Page 354: ... clock source begins its next cycle 0 PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled 1 Pulse width channel 0 is enabled The pulse modulated signal becomes available at PWM output bit 0 when its clock source begins its next cycle If CON01 1 then bit has no effect and PWM output line 0 is disabled Module Base 0x0001 7 6 5 4 3 2 1 0 R 0 0 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W ...

Page 355: ...nel 2 Polarity 0 PWM channel 2 output is low at the beginning of the period then goes high when the duty count is reached 1 PWM channel 2 output is high at the beginning of the period then goes low when the duty count is reached 1 PPOL1 Pulse Width Channel 1 Polarity 0 PWM channel 1 output is low at the beginning of the period then goes high when the duty count is reached 1 PWM channel 1 output is...

Page 356: ...l 5 4 PCLK4 Pulse Width Channel 4 Clock Select 0 Clock A is the clock source for PWM channel 4 1 Clock SA is the clock source for PWM channel 4 3 PCLK3 Pulse Width Channel 3 Clock Select 0 Clock B is the clock source for PWM channel 3 1 Clock SB is the clock source for PWM channel 3 2 PCLK2 Pulse Width Channel 2 Clock Select 0 Clock B is the clock source for PWM channel 2 1 Clock SB is the clock s...

Page 357: ...eld Descriptions Field Description 6 5 PCKB 2 0 Prescaler Select for Clock B Clock B is 1 of two clock sources which can be used for channels 2 or 3 These three bits determine the rate of clock B as shown in Table 12 6 2 0 PCKA 2 0 Prescaler Select for Clock A Clock A is 1 of two clock sources which can be used for channels 0 1 4 or 5 These three bits determine the rate of clock A as shown in Tabl...

Page 358: ...perates in left aligned output mode 1 Channel 5 operates in center aligned output mode 4 CAE4 Center Aligned Output Mode on Channel 4 0 Channel 4 operates in left aligned output mode 1 Channel 4 operates in center aligned output mode 3 CAE3 Center Aligned Output Mode on Channel 3 1 Channel 3 operates in left aligned output mode 1 Channel 3 operates in center aligned output mode 2 CAE2 Center Align...

Page 359: ...byte channel When channels 2 and 3 are concatenated channel 2 registers become the high order bytes of the double byte channel When channels 0 and 1 are concatenated channel 0 registers become the high order bytes of the double byte channel Reference Section 12 4 2 7 PWM 16 Bit Functions for a more detailed description of the concatenation PWM function NOTE Change these bits only when both corresp...

Page 360: ... and 1 are concatenated to create one 16 bit PWM channel Channel 0 becomes the high order byte and channel 1 becomes the low order byte Channel 1 output pin is used as the output for this 16 bit PWM bit 1 of port PWMP Channel 1 clock select control bit determines the clock source channel 1 polarity bit determines the polarity channel 1 enable bit enables the output and channel 1 center aligned ena...

Page 361: ...er the PWM functionality 12 3 2 8 Reserved Register PWMPRSC This register is reserved for factory testing of the PWM module and is not available in normal modes Read always read 0x0000 in normal modes Write unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality Module Base 0x0006 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Un...

Page 362: ...cale counter to load the PWMSCLA value 12 3 2 10 PWM Scale B Register PWMSCLB PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB Clock SB is generated by taking clock B dividing it by the value in the PWMSCLB register and dividing that by two Clock SB Clock B 2 PWMSCLB NOTE When PWMSCLB 0x0000 PWMSCLB value is considered a full scale value of 256 Clock B is thus d...

Page 363: ...ailable in normal modes Read always read 0x0000 in normal modes Write unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality Module Base 0x000A 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 12 13 Reserved Register PWMSCNTA Module Base 0x000B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 ...

Page 364: ...nd of the effective period see Section 12 4 2 5 Left Aligned Outputs and Section 12 4 2 6 Center Aligned Outputs for more details When the channel is disabled PWMEx 0 the PWMCNTx register does not count When a channel becomes enabled PWMEx 1 the associated PWM counter starts at the count in the PWMCNTx register For more detailed information on the operation of the counters reference Section 12 4 2...

Page 365: ...ake effect until one of the following occurs The effective period ends The counter is written counter resets to 0x0000 Module Base 0x000E 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 12 17 PWM Channel Counter Registers PWMCNT2 Module Base 0x000F 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Figure 12 18 PWM Channel Cou...

Page 366: ... information To calculate the output period take the selected clock source period for the channel of interest A B SA or SB and multiply it by the value in the period register for that channel Left aligned output CAEx 0 PWMx period channel clock period PWMPERx center aligned output CAEx 1 PWMx period channel clock period 2 PWMPERx For boundary case programming values please refer to Section 12 4 2 ...

Page 367: ...ffect until one of the following occurs The effective period ends The counter is written counter resets to 0x0000 The channel is disabled In this way the output of the PWM will always be either the old duty waveform or the new duty waveform not some variation in between If the channel is not enabled then writes to the duty register will go directly to the latches as well as the buffer Module Base ...

Page 368: ...ime If the polarity bit is 0 the output starts low and then goes high when the duty count is reached so the duty registers contain a count of the low time To calculate the output duty cycle high time as a of period for a particular channel Polarity 0 PPOLx 0 Duty cycle PWMPERx PWMDTYx PWMPERx 100 Polarity 1 PPOLx 1 Duty cycle PWMDTYx PWMPERx 100 For boundary case programming values please refer to...

Page 369: ... 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 1 1 1 1 1 1 1 1 Figure 12 30 PWM Channel Duty Registers PWMDTY3 Module Base 0x001C 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 1 1 1 1 1 1 1 1 Figure 12 31 PWM Channel Duty Registers PWMDTY4 Module Base 0x001D 7 6 5 4 3 2 1 0 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 1 1 1 1 1 1 1 1 Figure 12 32 PWM Channel Duty Registers PWMDTY5 Module Base 0x00E 7 6 5 4 3 2...

Page 370: ... corresponding counter passes next counter 0 phase Also if the PWM5ENA bit is reset to 0 the PWM do not start before the counter passes 0x0000 The bit is always read as 0 4 PWMLVL PWM Shutdown Output Level If active level as defined by the PWM5IN input gets asserted all enabled PWM channels are immediately driven to the level defined by PWMLVL 0 PWM outputs are forced to 0 1 PWM outputs are forced...

Page 371: ...k clock A or B or the scaled clock clock SA or SB The block diagram in Figure 12 34 shows the four different clocks and how the scaled clocks are created 12 4 1 1 Prescale The input clock to the PWM prescaler is the bus clock It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register If this bit is set whenever the MCU is in freeze mode the input clock to...

Page 372: ... SA Clock A 2 A 4 A 6 A 512 PRESCALE SCALE Divide by Prescaler Taps PFRZ FREEZE Bus Clock CLOCK SELECT M U X PCLK0 Clock to PWM Ch 0 M U X PCLK2 Clock to PWM Ch 2 M U X PCLK1 Clock to PWM Ch 1 M U X PCLK4 Clock to PWM Ch 4 M U X PCLK5 Clock to PWM Ch 5 M U X PCLK3 Clock to PWM Ch 3 Load DIV 2 PWMSCLB 8 Bit Down Counter Clock SB Clock B 2 B 4 B 6 B 512 M U X PCKA2 PCKA1 PCKA0 PWME5 0 Count 1 Load D...

Page 373: ... value is considered a full scale value of 256 Clock A is thus divided by 512 Similarly clock B is used as an input to an 8 bit down counter followed by a divide by two producing clock SB Thus clock SB equals clock B divided by two times the value in the PWMSCLB register NOTE Clock SB Clock B 2 PWMSCLB When PWMSCLB 0x0000 PWMSCLB value is considered a full scale value of 256 Clock B is thus divide...

Page 374: ...art of the PWM module are the actual timers Each of the timer channels has a counter a period register and a duty register each are 8 bit The waveform output period is controlled by a match between the period register and the value in the counter The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period The star...

Page 375: ...WMPOL register is set the associated PWM channel output is high at the beginning of the waveform then goes low when the duty count is reached Conversely if the polarity bit is 0 the output starts low and then goes high when the duty count is reached 12 4 2 3 PWM Period and Duty Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the chann...

Page 376: ... the counter stops When a channel becomes enabled PWMEx 1 the associated PWM counter continues from the count in the PWMCNTx register This allows the waveform to resume when the channel is re enabled When the channel is disabled writing 0 to the period register will cause the counter to reset on the next selected clock NOTE If the user wants to start a new clean PWM waveform without any history fr...

Page 377: ...r to the associated registers as described in Section 12 4 2 3 PWM Period and Duty The counter counts from 0 to the value in the period register 1 NOTE Changing the PWM output mode from left aligned output to center aligned output or vice versa while channels are operating can cause irregularities in the PWM output It is recommended to program the output mode before enabling the PWM channel Figure...

Page 378: ...eriod register changes the counter direction from an up count to a down count When the PWM counter decrements and matches the duty register again the output flip flop changes state causing the PWM output to also change state When the PWM counter decrements and reaches 0 the counter direction changes from a down count back to an up count and a load from the double buffer period and duty registers t...

Page 379: ...Aligned Output Example Waveform 12 4 2 7 PWM 16 Bit Functions The PWM timer also has the option of generating 6 channels of 8 bits or 3 channels of 16 bits for greater PWM resolution This 16 bit channel option is achieved through the concatenation of two 8 bit channels The PWMCTL register contains three control bits each of which is used to concatenate a pair of PWM channels into one 16 bit channe...

Page 380: ...ll After concatenated mode is enabled CONxx bits set in PWMCTL register enabling disabling the corresponding 16 bit PWM channel is controlled by the low order PWMEx bit In this case the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled In concatenated mode writes to the 16 bit counter by using a 16 bit access or writes to either the low or high order byte of...

Page 381: ...all the counters don t count 12 6 Interrupts The PWM8B6CV1 module has only one interrupt which is generated at the time of emergency shutdown if the corresponding enable bit PWMIE is set This bit is the enable for the interrupt The interrupt flag PWMIF is set whenever the input level of the PWM5 channel changes while PWM5ENA 1 or when PWMENA is being asserted while the level at PWM5 is active A de...

Page 382: ...Chapter 12 Pulse Width Modulator PWM8B6CV1 Block Description 382 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 383: ...st Significant Bit MSB Most Significant Bit NRZ Non Return to Zero RZI Return to Zero Inverted RXD Receive Pin SCI Serial Communication Interface TXD Transmit Pin 13 1 2 Features The SCI includes these distinctive features Full duplex operation Standard mark space non return to zero NRZ format 13 bit baud rate selection Programmable 8 bit or 9 bit data format Separately enabled transmitter and rec...

Page 384: ... CPU is in wait mode If SCISWAI is set SCI clock generation ceases and the SCI module enters a power conservation state when the CPU is in wait mode Setting SCISWAI does not affect the state of the receiver enable bit RE or the transmitter enable bit TE If SCISWAI is set any transmission or reception in progress stops at wait mode entry The transmission or reception resumes when either an internal...

Page 385: ... 2 External Signal Description The SCI module has a total of two external pins 13 2 1 TXD SCI Transmit Pin This pin serves as transmit data output of SCI 13 2 2 RXD SCI Receive Pin This pin serves as receive data input of the SCI SCI DATA REGISTER RECEIVE SHIFT REGISTER RECEIVE WAKE UP CONTROL DATA FORMAT CONTROL TRANSMIT CONTROL TRANSMIT SHIFT REGISTER SCI DATA REGISTER BAUD GENERATOR RX DATA IN ...

Page 386: ...n address order Each description includes a standard register diagram with an associated figure number Writes to a reserved register location do not have any effect and reads of these locations return a zero Details of register bit and field function follow the register diagrams in bit order Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 SCIBDH R 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x0001 SCIBDL R SB...

Page 387: ...written to as well following a write to SCIBDH Write Anytime Module Base 0x_0000 7 6 5 4 3 2 1 0 R 0 0 0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 0 0 0 0 0 Module Base 0x_0001 7 6 5 4 3 2 1 0 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W Reset 0 0 0 0 0 1 0 0 Unimplemented or Reserved Figure 13 3 SCI Baud Rate Registers SCIBDH and SCIBDL Table 13 1 SCIBDH AND SCIBDL Field Descriptions Field Descrip...

Page 388: ...r nine bits long 0 One start bit eight data bits one stop bit 1 One start bit nine data bits one stop bit 3 WAKE Wakeup Condition Bit WAKE determines which condition wakes up the SCI a logic 1 address mark in the most significant bit position of a received data character or an idle condition on the RXD 0 Idle line wakeup 1 Address mark wakeup 2 ILT Idle Line Type Bit ILT determines when the receiv...

Page 389: ...d 1 TDRE interrupt requests enabled 6 TCIE Transmission Complete Interrupt Enable Bit TCIE enables the transmission complete flag TC to generate interrupt requests 0 TC interrupt requests disabled 1 TC interrupt requests enabled 5 RIE Receiver Full Interrupt Enable Bit RIE enables the receive data register full flag RDRF or the overrun flag OR to generate interrupt requests 0 RDRF and OR interrupt...

Page 390: ... bits 0 No break characters 1 Transmit break characters Module Base 0x_0004 7 6 5 4 3 2 1 0 R TDRE TC RDRF IDLE OR NF FE PF W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 13 6 SCI Status Register 1 SCISR1 Table 13 5 SCISR1 Field Descriptions Field Description 7 TDRE Transmit Data Register Empty Flag TDRE is set when the transmit shift register receives a byte from the SCI data register W...

Page 391: ...when RDRF flag is clear This may happen if the following sequence of events occurs 1 After the first frame is received read status register SCISR1 returns RDRF set and OR flag clear 2 Receive second frame without reading the first frame in the data register the second frame is not received and OR flag is set 3 Read data register SCIDRL returns first frame and clears RDRF flag in the status registe...

Page 392: ...ransmit break character is 10 or 11 bit respectively 13 or 14 bits long The detection of a framing error is not affected by this bit 0 Break Character is 10 or 11 bit long 1 Break character is 13 or 14 bit long 1 TXDIR Transmitter Pin Data Direction in Single Wire Mode This bit determines whether the TXD pin is going to be used as an input or output in the Single Wire mode of operation This bit is...

Page 393: ...ing 8 bit write instructions write first to SCI data register high SCIDRH then SCIDRL Module Base 0x_0006 7 6 5 4 3 2 1 0 R R8 T8 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Module Base 0x_0007 7 6 5 4 3 2 1 0 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 13 8 SCI Data Registers SCIDRH and SCIDRL Table 13 7 SCIDRH AND SCIDRL Field Descriptions F...

Page 394: ...on between the CPU and remote devices including other CPUs The SCI transmitter and receiver operate independently although they use the same baud rate generator The CPU monitors the status of the SCI writes the data to be transmitted and processes received data Figure 13 9 SCI Block Diagram SCI DATA RECEIVE SHIFT REGISTER SCI DATA REGISTER TRANSMIT SHIFT REGISTER REGISTER BAUD RATE GENERATOR SBR12...

Page 395: ...he T8 bit in SCI data register high SCIDRH It remains unchanged after transmission and can be used repeatedly without rewriting it A frame with nine data bits has a total of 11 bits Table 13 9 Example of 9 Bit Data Formats Table 13 8 Example of 8 Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8 0 0 1 1 7 0 1 1 1 7 1 1 1 The address bit identifies the frame as an address c...

Page 396: ...ck divided by 16 drives the transmitter The receiver has an acquisition rate of 16 samples per bit time Baud rate generation is subject to one source of error Integer division of the module clock may not give the exact target frequency Table 13 10 lists some examples of achieving target baud rates with a module clock frequency of 25 MHz SCI baud rate SCI module clock 16 SCIBR 12 0 Table 13 10 Baud...

Page 397: ... shift register The transmit shift register then shifts a frame out through the Tx output signal after it has prefaced them with a start bit and appended them with a stop bit The SCI data registers SCIDRH and SCIDRL are the write only buffers between the internal data bus and the transmit shift register The SCI also sets a flag the transmit data register empty flag TDRE every time it transfers dat...

Page 398: ...he TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH L which happens generally speaking a little over half way through the stop bit of the previous frame Specifically this transfer occurs 9 16ths of a bit time AFTER the start of the stop bit of the previous frame Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with ...

Page 399: ...to the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic ...

Page 400: ...E bit is clear and the transmission is complete the SCI is not the master of the TXD pin 13 4 4 Receiver Figure 13 12 SCI Receiver Block Diagram 13 4 4 1 Receiver Character Length The SCI receiver can accommodate either 8 bit or 9 bit data characters The state of the M bit in SCI control register 1 SCICR1 determines the length of data characters When receiving 9 bit data bit R8 in SCI data registe...

Page 401: ... rate mismatch the RT clock see Figure 13 13 is re synchronized After every start bit After the receiver detects a data bit change from logic 1 to logic 0 after the majority of data bit samples at RT8 RT9 and RT10 returns a valid logic 1 and the majority of the next RT8 RT9 and RT10 samples returns a valid logic 0 To locate the start bit data recovery logic does an asynchronous search for a logic ...

Page 402: ...amples are logic 1s following a successful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit logic 0 To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 Table 13 13 summarizes the results of the stop bit samples Table 13 13 Stop Bit Recovery 100 Yes 1 101 No 0 110 No 0 111 No 0 Table 13 12 Data Bit Recovery RT...

Page 403: ... at RT3 is high The RT3 sample sets the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful Figure 13 15 Start Bit Search Example 2 RESET RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 SAMPLES RT CLOCK RT CLOCK COUNT START B...

Page 404: ...ure 13 17 shows the effect of noise early in the start bit time Although this noise does not affect proper synchronization with the start bit time it does set the noise flag Figure 13 17 Start Bit Search Example 4 RESET RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT13 RT12 RT11 RT16 RT15 RT14 RT4 RT3 RT2 RT1 RT5 RT6 RT7 RT8 RT9 SAMPLES RT CLOCK RT CLOCK COUNT ACTUAL START BIT Rx ...

Page 405: ...n Figure 13 19 a noise burst makes the majority of data samples RT8 RT9 and RT10 high This sets the noise flag but does not reset the RT clock In start bits only the RT8 RT9 and RT10 data samples are ignored Figure 13 19 Start Bit Search Example 6 RESET RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 SAMPLES RT CLOCK RT CLOCK...

Page 406: ...n any valid falling edge within the frame Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times 13 4 4 5 1 Slow Data Tolerance Figure 13 20 shows how much a slow received frame can be misaligned without causing a noise error or a framing error The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples...

Page 407: ...s 160 RTt cycles The maximum percent difference between the receiver count and the transmitter count of a fast 8 bit character with no errors is 160 154 160 x 100 3 75 For a 9 bit data character it takes the receiver 10 bit times x 16 RTr cycles 10 RTr cycles 170 RTr cycles to finish data sampling of the stop bit With the misaligned character shown in Figure 13 21 the receiver counts 170 RTr cycle...

Page 408: ...o message contains idle characters The idle character that wakes a receiver does not set the receiver idle bit IDLE or the receive data register full flag RDRF The idle line type bit ILT determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit ILT is in SCI control register 1 SCICR1 13 4 4 6 2 Address Mark Wakeup WAKE 1 In this wakeu...

Page 409: ...is going to be used as an input TXDIR 0 or an output TXDIR 1 in this mode of operation 13 4 6 Loop Operation In loop operation the transmitter output goes to the receiver input The Rx Input signal is disconnected from the SCI Figure 13 23 Loop Operation LOOPS 1 RSRC 0 Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 SCICR1 Setting the LOOPS bit dis...

Page 410: ...01 24 13 5 2 Interrupt Operation 13 5 2 1 System Level Interrupt Sources There are five interrupt sources that can generate an SCI interrupt in to the CPU They are listed in Table 13 14 Table 13 14 SCI Interrupt Source Interrupt Source Flag Local Enable Transmitter TDRE TIE Transmitter TC TCIE Receiver RDRF RIE OR Receiver IDLE ILIE ...

Page 411: ... Clear TC by reading SCI status register 1 SCISR1 with TC set and then writing to SCI data register low SCIDRL TC is cleared automatically when data preamble or break is queued and ready to be sent 13 5 2 2 3 RDRF Description The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register A RDRF interrupt indicates that the received data has been transferre...

Page 412: ...Chapter 13 Serial Communications Interface S12SCIV2 Block Description 412 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 413: ...t mode is a configurable low power mode controlled by the SPISWAI bit located in the SPICR2 register In wait mode if the SPISWAI bit is clear the SPI operates like in Run Mode If the SPISWAI bit is set the SPI goes into a power conservative state with the SPI clock generation turned off If the SPI is configured as a master any transmission in progress stops but is resumed after CPU goes into Run M...

Page 414: ...le has a total of four external pins 14 2 1 MOSI Master Out Slave In Pin This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave SPI Control Register 1 SPI Control Register 2 SPI Baud Rate Register SPI Status Register SPI Data Register Shifter Port Control Logic MOSI SCK Interrupt Control SPI MSB LSB LSBFE 1 LSBFE 0 ...

Page 415: ...ase of slave 14 3 Memory Map and Register Definition This section provides a detailed description of address space and registers used by the SPI The memory map for the SPIV3 is given below in Table 14 1 The address listed for each register is the sum of a base address and an address offset The base address is defined at the SoC level and the address offset is defined at the module level Reads from...

Page 416: ...4 3 2 1 SPI Control Register 1 SPICR1 Read anytime Write anytime Name 7 6 5 4 3 2 1 0 0x0000 SPICR1 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W 0x0001 SPICR2 R 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 W 0x0002 SPIBR R 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0 W 0x0003 SPISR R SPIF 0 SPTEF MODF 0 0 0 0 W 0x0004 Reserved R W 0x0005 SPIDR R Bit 7 6 5 4 3 2 2 Bit 0 W 0x0006 Reserved R W 0x0007 Reserved R W Uni...

Page 417: ...lues In master mode a change of this bit will abort a transmission in progress and force the SPI system into idle state 0 Active high clocks selected In idle state SCK is low 1 Active low clocks selected In idle state SCK is high 2 CPHA SPI Clock Phase Bit This bit is used to select the SPI clock format In master mode a change of this bit will abort a transmission in progress and force the SPI sys...

Page 418: ...he SPI 1 SS port pin with MODF feature 3 BIDIROE Output Enable in the Bidirectional Mode of Operation This bit controls the MOSI and MISO output buffer of the SPI when in bidirectional mode of operation SPC0 is set In master mode this bit controls the output buffer of the MOSI port in slave mode it controls the output buffer of the MISO port In master mode with SPC0 set a change of this bit will a...

Page 419: ...lemented or Reserved Figure 14 5 SPI Baud Rate Register SPIBR Table 14 6 SPIBR Field Descriptions Field Description 6 4 SPPR 2 0 SPI Baud Rate Preselection Bits These bits specify the SPI baud rates as shown in Table 14 7 In master mode a change of these bits will abort a transmission in progress and force the SPI system into idle state 2 0 SPR 2 0 SPI Baud Rate Selection Bits These bits specify t...

Page 420: ...Hz 0 0 1 0 1 1 32 781 25 kHz 0 0 1 1 0 0 64 390 63 kHz 0 0 1 1 0 1 128 195 31 kHz 0 0 1 1 1 0 256 97 66 kHz 0 0 1 1 1 1 512 48 83 kHz 0 1 0 0 0 0 6 4 16667 MHz 0 1 0 0 0 1 12 2 08333 MHz 0 1 0 0 1 0 24 1 04167 MHz 0 1 0 0 1 1 48 520 83 kHz 0 1 0 1 0 0 96 260 42 kHz 0 1 0 1 0 1 192 130 21 kHz 0 1 0 1 1 0 384 65 10 kHz 0 1 0 1 1 1 768 32 55 kHz 0 1 1 0 0 0 8 3 125 MHz 0 1 1 0 0 1 16 1 5625 MHz 0 1 1...

Page 421: ...768 32 55 kHz 1 0 1 1 1 1 1536 16 28 kHz 1 1 0 0 0 0 14 1 78571 MHz 1 1 0 0 0 1 28 892 86 kHz 1 1 0 0 1 0 56 446 43 kHz 1 1 0 0 1 1 112 223 21 kHz 1 1 0 1 0 0 224 111 61 kHz 1 1 0 1 0 1 448 55 80 kHz 1 1 0 1 1 0 896 27 90 kHz 1 1 0 1 1 1 1792 13 95 kHz 1 1 1 0 0 0 16 1 5625 MHz 1 1 1 0 0 1 32 781 25 kHz 1 1 1 0 1 0 64 390 63 kHz 1 1 1 0 1 1 128 195 31 kHz 1 1 1 1 0 0 256 97 66 kHz 1 1 1 1 0 1 512 ...

Page 422: ...R 5 SPTEF SPI Transmit Empty Interrupt Flag If set this bit indicates that the transmit data register is empty To clear this bit and place data into the transmit data register SPISR has to be read with SPTEF 1 followed by a write to SPIDR Any write to the SPI Data Register without reading SPTEF 1 is effectively ignored 0 SPI Data register not empty 1 SPI Data register empty 4 MODF Mode Fault Flag ...

Page 423: ...the slave are linked by the MOSI and MISO pins to form a distributed 16 bit register When a data transfer operation is performed this 16 bit register is serially shifted eight bit positions by the S clock from the master so data is exchanged between the master and the slave Data written to the master SPI Data Register becomes the output data for the slave and data read from the master SPI Data Reg...

Page 424: ... is set and SSOE is cleared the SS pin is configured as input for detecting mode fault error If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines In this case the SPI immediately switches to slave mode by clearing the MSTR bit and also disables the slave output buffer MISO or SISO in bidirectional mode So the result is that all ou...

Page 425: ...e two receivers whose serial outputs drive the same system slave s serial data output line As long as no more than one slave device drives the system slave s serial data output line it is possible for several slaves to receive the same transmission from a master although the master would not receive return information from all of the receiving slaves If the CPHA bit in SPI Control Register 1 is cl...

Page 426: ...se and polarity should be identical for the master SPI device and the communicating slave device In some cases the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements 14 4 3 2 CPHA 0 Transfer Format The first edge on the SCK line is used to clock the first data bit of the slave into the master and the fir...

Page 427: ... the master The SS pin of the master must be either high or reconfigured as a general purpose output not affecting the SPI Figure 14 9 SPI Clock Format 0 CPHA 0 In slave mode if the SS line is not deasserted between the successive transmissions then the content of the SPI Data Register is not transmitted instead the last received byte is transmitted If the SS line is deasserted for at least minimu...

Page 428: ...ng taking place on odd numbered edges Data reception is double buffered data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in After the 16th SCK edge Data that was previously in the SPI Data Register of the master is now in the data register of the slave and data that was in the data register o...

Page 429: ...odule clock divisor becomes 8 etc When the preselection bits are 001 the divisor determined by the selection bits is multiplied by 2 When the preselection bits are 010 the divisor is multiplied by 3 etc See Table 14 7 for baud rate calculations for all bit conditions based on a 25 MHz bus clock The two sets of selects allows the clock to be divided by a non power of two to achieve other baud rates...

Page 430: ... is disabled while SS output is enabled NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters 14 4 5 2 Bidirectional Mode MOSI or MISO The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 see Table 14 9 In this mode the SPI uses only one serial dat...

Page 431: ...error where more than one master may be trying to drive the MOSI and SCK lines simultaneously This condition is not permitted in normal operation the MODF bit in the SPI Status Register is set automatically provided the MODFEN bit is set In the special case where the SPI is in master mode and MODFEN bit is cleared the SS pin is not used by the SPI In this special case the mode fault error function...

Page 432: ...l continue to send out bytes consistent with the operation mode at the start of wait mode i e If the slave is currently sending its SPIDR to the master it will continue to send the same byte Else if the slave is currently sending the last received byte from the master it will continue to send each previous master byte NOTE Care must be taken when expecting data from a master while the slave is in ...

Page 433: ...n error on the SS pin The master SPI must be configured for the MODF feature see Table 14 3 After MODF is set the current transfer is aborted and the following bit is changed MSTR 0 The master bit in SPICR1 resets The MODF interrupt is reflected in the status register MODF flag Clearing the flag will also clear the interrupt This interrupt will stay active while the MODF flag is set MODF has an au...

Page 434: ...Chapter 14 Serial Peripheral Interface SPIV3 Block Description 434 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 435: ...d time accumulator The pulse accumulator shares timer channel 7 when in event mode A full access for the counter registers or the input capture output compare registers should take place in one clock cycle Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word 15 1 1 Features The TIM16B8CV1 includes these distinctive featu...

Page 436: ...eared to 0 15 1 3 Block Diagrams Figure 15 1 TIM16B8CV1 Block Diagram Prescaler 16 bit Counter Input capture Output compare 16 bit Pulse accumulator IOC0 IOC2 IOC1 IOC5 IOC3 IOC4 IOC6 IOC7 PA input interrupt PA overflow interrupt Timer overflow interrupt Timer channel 0 interrupt Timer channel 7 interrupt Registers Bus clock Input capture Output compare Input capture Output compare Input capture O...

Page 437: ... 2 16 Bit Pulse Accumulator Block Diagram Figure 15 3 Interrupt Flag Setting Edge detector Intermodule Bus PT7 M clock Divide by 64 Clock select CLK0 CLK1 4 1 MUX TIMCLK PACLK PACLK 256 PACLK 65536 Prescaled clock PCLK Timer clock Interrupt MUX PAMOD PACNT PTn Edge detector 16 bit Main Timer TCn Input Capture Reg Set CnF Interrupt ...

Page 438: ...rves as input capture or output compare for channel 7 This can also be configured as pulse accumulator input 15 2 2 IOC6 Input Capture and Output Compare Channel 6 Pin This pin serves as input capture or output compare for channel 6 15 2 3 IOC5 Input Capture and Output Compare Channel 5 Pin This pin serves as input capture or output compare for channel 5 15 2 4 IOC4 Input Capture and Output Compar...

Page 439: ...0 Input Capture and Output Compare Channel 0 Pin This pin serves as input capture or output compare for channel 0 NOTE For the description of interrupts see Section 15 6 Interrupts 15 3 Memory Map and Register Definition This section provides a detailed description of all memory and registers 15 3 1 Module Memory Map The memory map for the TIM16B8CV1 module is given below in Table 15 2 The address...

Page 440: ...x0011 Timer Input Capture Output Compare Register 0 TC0 lo R W3 0x0012 Timer Input Capture Output Compare Register 1 TC1 hi R W3 0x0013 Timer Input Capture Output Compare Register 1 TC1 lo R W3 0x0014 Timer Input Capture Output Compare Register 2 TC2 hi R W3 0x0015 Timer Input Capture Output Compare Register 2 TC2 lo R W3 0x0016 Timer Input Capture Output Compare Register 3 TC3 hi R W3 0x0017 Time...

Page 441: ...OC4 FOC3 FOC2 FOC1 FOC0 0x0002 OC7M R OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 W 0x0003 OC7D R OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 W 0x0004 TCNTH R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W 0x0005 TCNTL R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W 0x0006 TSCR1 R TEN TSWAI TSFRZ TFFCA 0 0 0 0 W 0x0007 TTOV R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 W 0x0008 TC...

Page 442: ...R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0020 PACTL R 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI W 0x0021 PAFLG R 0 0 0 0 0 0 PAOVF PAIF W 0x0022 PACNTH R PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 W 0x0023 PACNTL R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W 0x0024 0x002F Reserved R W Module Base 0x0000 7 6 5 4 3 2 1 0 R IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1...

Page 443: ... 0 0 Figure 15 7 Timer Compare Force Register CFORC Table 15 4 CFORC Field Descriptions Field Description 7 0 FOC 7 0 Force Output Compare Action for Channel 7 0 A write to this register with the corresponding data bit s set causes the action which is programmed for output compare x to occur immediately The action taken is the same as if a successful comparison had just taken place with the TCx re...

Page 444: ...et the output compare action reflects the corresponding OC7D bit Module Base 0x0003 7 6 5 4 3 2 1 0 R OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 W Reset 0 0 0 0 0 0 0 0 Figure 15 9 Output Compare 7 Data Register OC7D Table 15 6 OC7D Field Descriptions Field Description 7 0 OC7D 7 0 Output Compare 7 Data A channel 7 output compare can cause bits in the output compare 7 data register to transfe...

Page 445: ...tem Control Register 1 TSCR1 Read Anytime Write Anytime Module Base 0x0006 7 6 5 4 3 2 1 0 R TEN TSWAI TSFRZ TFFCA 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 15 12 Timer System Control Register 1 TSCR1 Table 15 7 TSCR1 Field Descriptions Field Description 7 TEN Timer Enable 0 Disables the main timer including the counter Can be used for reducing power consumption 1 Allows the...

Page 446: ...TOF flag Any access to the PACNT registers 0x0022 0x0023 clears the PAOVF and PAIF flags in the PAFLG register 0x0021 This has the advantage of eliminating software overhead in a separate clear sequence Extra care is required to avoid accidental flag clearing due to unintended accesses Module Base 0x0007 7 6 5 4 3 2 1 0 R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 W Reset 0 0 0 0 0 0 0 0 Figure 15 13...

Page 447: ... to specify the output action to be taken as a result of a successful OCx compare When either OMx or OLx is 1 the pin associated with OCx becomes an output tied to OCx Note To enable output action by OMx bits on timer port the corresponding bit in OC7M should be cleared 7 0 OLx Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a succ...

Page 448: ...le 15 11 the IOS7 and IOSx should be set to 1 IOSx is the register TIOS bit x OC7Mx is the register OC7M bit x TCx is timer Input Capture Output Compare register IOCx is channel x OMx OLx is the register TCTL1 TCTL2 OC7Dx is the register OC7D bit x IOCx OC7Dx OMx OLx means that both OC7 event and OCx event will change channel x value ...

Page 449: ...Register 3 TCTL3 Module Base 0x000B 7 6 5 4 3 2 1 0 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A W Reset 0 0 0 0 0 0 0 0 Figure 15 17 Timer Control Register 4 TCTL4 Table 15 12 TCTL3 TCTL4 Field Descriptions Field Description 7 0 EDGnB EDGnA Input Capture Edge Control These eight pairs of control bits configure the input capture edge detector circuits Table 15 13 Edge Detector Circuit Configu...

Page 450: ... 0 0 0 Figure 15 18 Timer Interrupt Enable Register TIE Table 15 14 TIE Field Descriptions Field Description 7 0 C7I C0I Input Capture Output Compare x Interrupt Enable The bits in TIE correspond bit for bit with the bits in the TFLG1 status register If cleared the corresponding flag is disabled from causing a hardware interrupt If set the corresponding flag is enabled to cause a interrupt Module ...

Page 451: ...d and counter free runs 1 Counter reset by a successful output compare 7 Note If TC7 0x0000 and TCRE 1 TCNT will stay at 0x0000 continuously If TC7 0xFFFF and TCRE 1 TOF will never be set when TCNT is reset from 0xFFFF to 0x0000 Note TCRE 1 and TC7 0 the TCNT cycle period will be TC7 x prescaler counter width 1 Bus Clock for a more detail explanation please refer to Section 15 4 3 Output Compare 2...

Page 452: ...ptions Field Description 7 0 C 7 0 F Input Capture Output Compare Channel x Flag These flags are set when an input capture or output compare event occurs Clearing requires writing a one to the corresponding flag bit when TEN is set to one When TFFCA bit in TSCR register is set a read from an input capture or a write into an output compare channel 0x0010 0x001F will cause the corresponding channel ...

Page 453: ...r effect during input capture All timer input capture output compare registers are reset to 0x0000 NOTE Read Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result Module Base 0x0010 TC0H 0x0012 TC1H 0x0014 TC2H 0x0016 TC3H 0x0018 TC4H 0x001A TC5H 0x001C TC6H 0x001E TC7H 15 14 13 12 11 10 9 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 ...

Page 454: ...it is active only when the Pulse Accumulator is enabled PAEN 1 See Table 15 20 0 Event counter mode 1 Gated time accumulation mode 4 PEDGE Pulse Accumulator Edge Control This bit is active only when the Pulse Accumulator is enabled PAEN 1 For PAMOD bit 0 event counter mode See Table 15 20 0 Falling edges on IOC7 pin cause the count to be incremented 1 Rising edges on IOC7 pin cause the count to be...

Page 455: ... Write Anytime When the TFFCA bit in the TSCR register is set any access to the PACNT register will clear all the flags in the PAFLG register Timer module must stay enabled TEN 1 while clearing thse bits Table 15 20 Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div by 64 clock enabled with pin high level 1 1 Div by 64 clock enabled with pin low level Table 15 21 Timer Cloc...

Page 456: ...G register while TEN bit of TSCR1 register is set to one 0 PAIF Pulse Accumulator Input edge Flag Set when the selected edge is detected at the IOC7 input pin In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the IOC7 input pin triggers PAIF Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit ...

Page 457: ...TE Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the bus clock first 15 4 Functional Description This section provides a complete functional description of the timer TIM16B8CV1 block Please refer to the detailed timer block diagram in Figure 15 28 as necessary...

Page 458: ...F PEDGE PAOVI TEN PAE 16 BIT COMPARATOR TCNT hi TCNT lo CHANNEL 1 TC1 16 BIT COMPARATOR 16 BIT COUNTER INTERRUPT LOGIC TOF TOI C0F C1F EDGE DETECT IOC1 PIN LOGIC EDGE DETECT CxF CHANNEL7 TC7 16 BIT COMPARATOR C7F IOC7 PIN LOGIC EDGE DETECT OM OL0 TOV0 OM OL1 TOV1 OM O73 TOV7 EDG1A EDG1B EDG7A EDG7B EDG0B TCRE PAIF CLEAR COUNTER PAIF PAI INTERRUPT LOGIC CxI INTERRUPT REQUEST PAOVF CH 7 COMPARE CH 7...

Page 459: ...pin An output compare on channel x sets the CxF flag The CxI bit enables the CxF flag to generate interrupt requests Timer module must stay enabled TEN bit of TSCR1 register must be set to one while clearing CxF writing one to CxF The output mode and level bits OMx and OLx select set clear toggle on output compare Clearing both OMx and OLx disconnects the pin from the output logic Setting a force ...

Page 460: ...e PACNT for event counter operation An active edge on the IOC7 pin increments the pulse accumulator counter The PEDGE bit selects falling edges or rising edges to increment the count NOTE The PACNT input and timer channel 7 use the same pin IOC7 To use the IOC7 disconnect it from the output logic by clearing the channel 7 output mode and output level bits OM7 and OL7 Also clear the channel 7 outpu...

Page 461: ...ck 15 5 Resets The reset state of each individual bit is listed within Section 15 3 Memory Map and Register Definition which details the registers and their bit fields 15 6 Interrupts This section describes interrupts originated by the TIM16B8CV1 block Table 15 23 lists the interrupts generated by the TIM16B8CV1 to communicate with the MCU The TIM16B8CV1 uses a total of 11 interrupt vectors The in...

Page 462: ... pulse accumulator input interrupt to be serviced by the system controller 15 6 3 Pulse Accumulator Overflow Interrupt PAOVF This active high output will be asserted by the module to request a timer pulse accumulator overflow interrupt to be serviced by the system controller 15 6 4 Timer Overflow Interrupt TOF This active high output will be asserted by the module to request a timer overflow inter...

Page 463: ... mode The regulator is active providing the nominal supply voltage of 2 5 V with full current sourcing capability at both outputs Features LVD low voltage detect LVR low voltage reset and POR power on reset are available Reduced power mode RPM MCU is in stop mode The purpose is to reduce power consumption of the device The output voltage may degrade to a lower value than in full performance mode a...

Page 464: ...inciple of VREG3V3V2 by means of a block diagram The regulator core REG consists of two parallel sub blocks REG1 and REG2 providing two independent output voltages Figure 16 1 VREG3V3 Block Diagram LVR LVD POR VDDR VDD LVI POR LVR CTRL VSS VDDPLL VSSPLL VREGEN REG REG2 REG1 PIN VDDA VSSA REG Regulator Core LVD Low Voltage Detect CTRL Regulator Control LVR Low Voltage Reset POR Power on Reset ...

Page 465: ...moothen ripple on VDDR For entering Shutdown Mode pin VDDR should also be tied to ground on devices without a VREGEN pin 16 2 2 VDDA VSSA Regulator Reference Supply Signals VDDA VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator Internal precision reference circuits are supplied from these signals A chip external decoupling capacitor 100 nF 220 nF X...

Page 466: ... capacitors 100 nF 220 nF X7R ceramic In Shutdown Mode an external supply at VDDPLL VSSPLL can replace the voltage regulator 16 2 5 VREGEN Optional Regulator Enable This optional signal is used to shutdown VREG3V3V2 In that case VDD VSS and VDDPLL VSSPLL must be provided externally Shutdown Mode is entered with VREGEN being low If VREGEN is high the VREG3V3V2 is either in Full Performance Mode or ...

Page 467: ...lator control block CTRL which represents the interface to the digital core logic but also manages the operating modes of VREG3V3V2 Module Base 0x0000 7 6 5 4 3 2 1 0 R 0 0 0 0 0 LVDS LVIE LVIF W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 16 2 VREG3V3 Control Register VREGCTRL Table 16 3 MCCTL1 Field Descriptions Field Description 2 LVDS Low Voltage Detect Status Bit This read only sta...

Page 468: ...ed to a buffered fraction of the input voltage VDDR The operational amplifier and the bandgap are disabled to reduce power consumption 16 4 4 LVD Low Voltage Detect sub block LVD is responsible for generating the low voltage interrupt LVI LVD monitors the input voltage VDDA VSSA and continuously updates the status flag LVDS Interrupt flag LVIF is set whenever status flag LVDS changes its value The...

Page 469: ...Reset For details on low voltage reset see Section 16 4 6 LVR Low Voltage Reset 16 6 Interrupts This subsection describes all interrupts originated by VREG3V3V2 The interrupt vectors requested by VREG3V3V2 are listed in Table 16 5 Vector addresses and interrupt priorities are defined at MCU level 16 6 1 LVI Low Voltage Interrupt In FPM VREG3V3V2 monitors the input voltage VDDA Whenever VDDA drops ...

Page 470: ...Chapter 16 Dual Output Voltage Regulator VREG3V3V2 Block Description 470 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 471: ... sector erase An erased bit reads 1 and a programmed bit reads 0 The high voltage required to program and erase is generated internally It is not possible to read from a Flash array while it is being erased or programmed CAUTION A Flash word must be in the erased state before being programmed Cumulative programming of bits within a Flash word is not allowed 17 1 1 Glossary Command Write Sequence A...

Page 472: ...7 4 1 Flash Command Operations 17 1 4 Block Diagram Figure 17 1 shows a block diagram of the FTS16K module Figure 17 1 FTS16K Block Diagram 17 2 External Signal Description The FTS16K module contains no signals that connect off chip FTS16K Oscillator Clock Command Complete Interrupt Command Buffer Empty Interrupt Flash Array 8K 16 Bits sector 0 sector 1 sector 31 Clock Divider FCLK Protection Secu...

Page 473: ...ash array or one growing downward from the Flash array end address The higher address area is mainly targeted to hold the boot loader code since it covers the vector space Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field described in Table 17 1 1 By placing 0x3F in the HCS12 Core PPAGE...

Page 474: ...F 0x3F 0xB800 0xBFFF 0xB000 0xBFFF 0xA000 0xBFFF 0x8000 0xBFFF 0xC000 0xFFFF Unpaged 0x3F 0xF800 0xFFFF 0xF000 0xFFFF 0xE000 0xFFFF 0xC000 0xFFFF Flash Registers MODULE BASE 0x0000 0xFF00 0xFF0F Flash Configuration Field MODULE BASE 0x000F 0x8000 16K PAGED MEMORY 0x3F Note 0x3F corresponds to the PPAGE register content FLASH_END 0xFFFF 0xF800 0xF000 FLASH_START 0xC000 0xE000 Flash Protected High S...

Page 475: ... R KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 W 0x0002 RESERVED1 1 1 Intended for factory test purposes only R 0 0 0 0 0 0 0 0 W 0x0003 FCNFG R CBEIE CCIE KEYACC 0 0 0 0 0 W 0x0004 FPROT R FPOPEN NV6 FPHDIS FPHS1 FPHS0 NV2 NV1 NV0 W 0x0005 FSTAT R CBEIF CCIF PVIOL ACCERR 0 BLANK FAIL DONE W 0x0006 FCMD R 0 CMDB6 CMDB5 0 0 CMDB2 0 CMDB0 W 0x0007 RESERVED21 R 0 0 0 0 0 0 0 0 W 0x0008 FADDRHI1 R 0 0 0 F...

Page 476: ... FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 17 4 Flash Clock Divider Register FCLKDIV Table 17 3 FCLKDIV Field Descriptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset 6 PRDIV8 Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flash...

Page 477: ... 5 2 NV 5 2 Nonvolatile Flag Bits The NV 5 2 bits are available to the user as nonvolatile flags 1 0 SEC 1 0 Flash Security Bits The SEC 1 0 bits define the security state of the MCU as shown in Table 17 6 If the Flash module is unsecured using backdoor key access the SEC 1 0 bits are forced to 1 0 Table 17 5 Flash KEYEN States KEYEN 1 0 Status of Backdoor Key Access 00 DISABLED 01 1 1 Preferred K...

Page 478: ... 2 1 0 R CBEIE CCIE KEYACC 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 17 7 Flash Configuration Register FCNFG Table 17 7 FCNFG Field Descriptions Field Description 7 CBEIE Command Buffer Empty Interrupt Enable The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requeste...

Page 479: ...the same address range to be unprotected as shown in Table 17 9 0 The FPHDIS bit allows a Flash address range to be unprotected 1 The FPHDIS bit allows a Flash address range to be protected 6 NV6 Nonvolatile Flag Bit The NV6 bit should remain in the erased state for future enhancements 5 FPHDIS Flash Protection Higher Address Range Disable The FPHDIS bit determines whether there is a protected unp...

Page 480: ...gure 17 9 Flash Protection Scenarios 17 3 2 5 1 Flash Protection Restrictions The general guideline is that protection can only be added not removed All valid transitions between Flash protection scenarios are specified in Table 17 11 Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged The contents of the FPROT register reflec...

Page 481: ...e started The CBEIF flag is cleared by writing a 1 to CBEIF Writing a 0 to the CBEIF flag has no effect on CBEIF Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag T...

Page 482: ...sible to launch another command 0 No access error detected 1 Access error has occurred 2 BLANK Flash Array Has Been Verified as Erased The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence Writing to the BLANK flag has no effect on BLANK 0 ...

Page 483: ...MDB 6 5 CMDB 2 CMDB 0 Valid Flash commands are shown in Table 17 14 An attempt to execute any command other than those listed in Table 17 14 will set the ACCERR bit in the FSTAT register see Section 17 3 2 6 Table 17 14 Valid Flash Command List CMDB NVM Command 0x05 Erase verify 0x20 Word program 0x40 Sector erase 0x41 Mass erase Module Base 0x0007 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0...

Page 484: ... data registers In normal modes all FDATAHI and FDATALO bits read 0 and are not writable In special modes all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range 17 3 2 11 RESERVED3 This register is reserved for factory testing and is not accessible to the user Module Base 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 0 0 0 0 Figure 17 14 F...

Page 485: ...ing and is not accessible to the user All bits read 0 and are not writable 17 3 2 14 RESERVED6 This register is reserved for factory testing and is not accessible to the user Module Base 0x000C 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 17 17 RESERVED3 Module Base 0x000D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reser...

Page 486: ...etween two programming commands The pipelined operation also allows a simplification of command launching Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated if enabled The next sections describe How to write the FCLKDIV register Command write sequence used to program erase or erase verify the Flash array Valid Flash comma...

Page 487: ...tion on the accuracy of the functional timings programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz Programming or erasing the Flash array with an input clock 150 kHz should be avoided Setting FCLKDIV to a value such that FCLK 150 kHz can destroy the Flash array due to overstress Setting FCLKDIV to a value such that 1 FCLK Tbus 5µs can result in incom...

Page 488: ...yes no PRDIV8 0 reset 12 8MHz FCLK PRDCLK 1 FDIV 5 0 PRDCLK oscillator_clock PRDCLK oscillator_clock 8 PRDCLK MHz 5 Tbus µs no FDIV 5 0 PRDCLK MHz 5 Tbus µs 1 yes START Tbus 1µs an integer FDIV 5 0 INT PRDCLK MHz 5 Tbus µs 1 FCLK MHz Tbus µs 5 AND FCLK 0 15MHz END yes no FDIV 5 0 4 ALL COMMANDS IMPOSSIBLE yes no ALL COMMANDS IMPOSSIBLE no TRY TO DECREASE Tbus yes oscillator_clock ...

Page 489: ...steps However Flash register and array reads are allowed during a command write sequence The basic command write sequence is as follows 1 Write to a valid address in the Flash array memory 2 Write a valid command to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command The address written in step 1 will be stored in the FADDR registers and the...

Page 490: ...word is not allowed Table 17 15 Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased If the Flash array is erased the BLANK bit will set in the FSTAT register upon command completion 0x20 Program Program a word 2 bytes in the Flash array 0x40 Sector Erase Erase all 512 bytes in a sector of the Flash array 0x41 Mass Erase Erase a...

Page 491: ... written will be ignored 2 Write the erase verify command 0x05 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command After launching the erase verify command the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered Upon completion of the erase verify op...

Page 492: ...x30 Write FSTAT register yes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CCIF Set ACCERR PVIOL Set no Erase Verify Status yes EXIT Flash Array Not Erased EXIT Flash Array Erased BLANK Set Write FCLKDIV register Read FCLKDIV registe...

Page 493: ...ogram command 0x20 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command If a word to be programmed is in a protected area of the Flash array the PVIOL flag in the FSTAT register will set and the program command will not launch Once the program command has successfully launched the CCIF flag in the FSTAT register will set after the ...

Page 494: ... no Access Error and Protection Violation no and program Data Bit Polling for Buffer Empty Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CBEIF Set ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset no yes Sequenti...

Page 495: ...the sector erase command The Flash address written determines the sector to be erased while MCU address bits 8 0 and the data written are ignored 2 Write the sector erase command 0x40 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command If a Flash sector to be erased is in a protected area of the Flash array the PVIOL flag in ...

Page 496: ...lear CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset...

Page 497: ...tart the command write sequence for the mass erase command The address and data written will be ignored 2 Write the mass erase command 0x41 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command If a Flash array to be erased contains any protected area the PVIOL flag in the FSTAT register will set and the mass erase command will n...

Page 498: ...ar CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset n...

Page 499: ...ding command is killed 10 When security is enabled a command other than mass erase originating from a non secure memory or from the background debug mode is written to the FCMD register 11 A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence The ACCERR flag will not be set if any Flash register is read during the command write sequence If the Flash array is read ...

Page 500: ...le 17 15 can be executed If the MCU is secured and is in special single chip mode the only possible command to execute is mass erase 17 4 3 Flash Module Security The Flash module provides the necessary security information to the MCU After each reset the Flash module determines the security state of the MCU as defined in Section 17 3 2 2 Flash Security Register FSEC The contents of the Flash secur...

Page 501: ...security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted The following illegal operations will lock the security state machine 1 If any of the four 16 bit words does not match the backdoor key programmed in the Flash array 2 If the four 16 bit words are written in the wrong sequence 3 If more than four 16 bit words are written 4 If any of the four ...

Page 502: ...s have completed execution or the Flash address data and command buffers are empty NOTE Vector addresses and their relative interrupt priority are determined at the MCU level 17 4 5 1 Description of Interrupt Operation Figure 17 26 shows the logic used for generating interrupts The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the ...

Page 503: ... sector erase An erased bit reads 1 and a programmed bit reads 0 The high voltage required to program and erase is generated internally It is not possible to read from a Flash array while it is being erased or programmed CAUTION A Flash word must be in the erased state before being programmed Cumulative programming of bits within a Flash word is not allowed 18 1 1 Glossary Command Write Sequence A...

Page 504: ...8 4 1 Flash Command Operations 18 1 4 Block Diagram Figure 18 1 shows a block diagram of the FTS32K module Figure 18 1 FTS32K Block Diagram 18 2 External Signal Description The FTS32K module contains no signals that connect off chip FTS32K Oscillator Clock Command Complete Interrupt Command Buffer Empty Interrupt Flash Array 16K 16 Bits sector 0 sector 1 sector 63 Clock Divider FCLK Protection Sec...

Page 505: ...can be activated for protection The Flash array addresses covered by these protectable regions are shown in Figure 18 2 The higher address area is mainly targeted to hold the boot loader code since it covers the vector space The lower address area can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from pr...

Page 506: ...x0000 0xFF00 0xFF0F Flash Configuration Field MODULE BASE 0x000F 0x8000 Flash Protected Low Sectors 512 bytes 1 2 4 Kbytes FLASH_START 0x4000 0x4800 0x4200 0x5000 16K PAGED MEMORY 0x3E 003E 0x3F Note 0x3E 0x3F correspond to the PPAGE register content FLASH_END 0xFFFF 0xF800 0xF000 0xC000 0xE000 Flash Protected High Sectors 2 4 8 16 Kbytes 0x3F 0x4400 Flash Array 16 bytes ...

Page 507: ...Array Relative Address 1 1 Inside Flash block 0x4000 0x7FFF Unpaged 0x3E 0x4000 0x43FF N A 0x18000 0x1BFFF 0x4000 0x47FF 0x4000 0x4FFF 0x4000 0x5FFF 0x8000 0xBFFF 0x3E 0x8000 0x83FF N A 0x18000 0x1BFFF 0x8000 0x87FF 0x8000 0x8FFF 0x8000 0x9FFF 0x3F N A 0xB800 0xBFFF 0x1C000 0x1FFFF 0xB000 0xBFFF 0xA000 0xBFFF 0x8000 0xBFFF 0xC000 0xFFFF Unpaged 0x3F N A 0xF800 0xFFFF 0x1C000 0x1FFFF 0xF000 0xFFFF ...

Page 508: ... KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 W 0x0002 RESERVED1 1 1 Intended for factory test purposes only R 0 0 0 0 0 0 0 0 W 0x0003 FCNFG R CBEIE CCIE KEYACC 0 0 0 0 0 W 0x0004 FPROT R FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0005 FSTAT R CBEIF CCIF PVIOL ACCERR 0 BLANK FAIL DONE W 0x0006 FCMD R 0 CMDB6 CMDB5 0 0 CMDB2 0 CMDB0 W 0x0007 RESERVED21 R 0 0 0 0 0 0 0 0 W 0x0008 FADDRHI1 R 0 ...

Page 509: ... FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 4 Flash Clock Divider Register FCLKDIV Table 18 3 FCLKDIV Field Descriptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset 6 PRDIV8 Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flash...

Page 510: ... 5 2 NV 5 2 Nonvolatile Flag Bits The NV 5 2 bits are available to the user as nonvolatile flags 1 0 SEC 1 0 Flash Security Bits The SEC 1 0 bits define the security state of the MCU as shown in Table 18 6 If the Flash module is unsecured using backdoor key access the SEC 1 0 bits are forced to 1 0 Table 18 5 Flash KEYEN States KEYEN 1 0 Status of Backdoor Key Access 00 DISABLED 01 1 1 Preferred K...

Page 511: ...eset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 7 Flash Configuration Register FCNFG Table 18 7 FCNFG Field Descriptions Field Description 7 CBEIE Command Buffer Empty Interrupt Enable The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requested whenever the CBEIF flag is set see Sec...

Page 512: ...ange specified by the corresponding FPxS 1 0 bits When FPOPEN is cleared FPxDIS defines unprotected ranges as specified by the corresponding FPxS 1 0 bits In this case setting FPxDIS enables protection Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as shown in Table 18 9 This function allows the main part of the Flash array to be protected while a small range can remai...

Page 513: ...LS 0 Function 1 1 For range sizes refer to Table 18 10 and or Table 18 11 1 1 x x 1 x x No protection 1 1 x x 0 x x Protect low range 1 0 x x 1 x x Protect high range 1 0 x x 0 x x Protect high and low ranges 0 1 x x 1 x x Full Flash array protected 0 0 x x 1 x x Unprotected high range 0 1 x x 0 x x Unprotected low range 0 0 x x 0 x x Unprotected high and low ranges Table 18 10 Flash Protection Hi...

Page 514: ... 12 Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged The contents of the FPROT register reflect the active protection scenario Table 18 12 Flash Protection Scenario Transitions From Protection Scenario To Protection Scenario 1 0 1 2 3 4 5 6 7 0 X X X X 1 X X 2 X X 3 X 4 X X 5 X X X X 7 6 5 4 FPOPEN 1 3 2 1 0 FPHS 1 0 FPLS 1...

Page 515: ...can be started The CBEIF flag is cleared by writing a 1 to CBEIF Writing a 0 to the CBEIF flag has no effect on CBEIF Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR f...

Page 516: ...sible to launch another command 0 No access error detected 1 Access error has occurred 2 BLANK Flash Array Has Been Verified as Erased The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence Writing to the BLANK flag has no effect on BLANK 0 ...

Page 517: ...CMDB 6 5 CMDB 2 CMDB 0 Valid Flash commands are shown in Table 18 15 An attempt to execute any command other than those listed in Table 18 15 will set the ACCERR bit in the FSTAT register see Section 18 3 2 6 Table 18 15 Valid Flash Command List CMDB NVM Command 0x05 Erase verify 0x20 Word program 0x40 Sector erase 0x41 Mass erase Module Base 0x0007 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 ...

Page 518: ... data registers In normal modes all FDATAHI and FDATALO bits read 0 and are not writable In special modes all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range 18 3 2 11 RESERVED3 This register is reserved for factory testing and is not accessible to the user Module Base 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 0 0 0 0 Figure 18 14 F...

Page 519: ...ing and is not accessible to the user All bits read 0 and are not writable 18 3 2 14 RESERVED6 This register is reserved for factory testing and is not accessible to the user Module Base 0x000C 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 17 RESERVED3 Module Base 0x000D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reser...

Page 520: ...etween two programming commands The pipelined operation also allows a simplification of command launching Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated if enabled The next sections describe How to write the FCLKDIV register Command write sequence used to program erase or erase verify the Flash array Valid Flash comma...

Page 521: ...tion on the accuracy of the functional timings programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz Programming or erasing the Flash array with an input clock 150 kHz should be avoided Setting FCLKDIV to a value such that FCLK 150 kHz can destroy the Flash array due to overstress Setting FCLKDIV to a value such that 1 FCLK Tbus 5µs can result in incom...

Page 522: ...yes no PRDIV8 0 reset 12 8MHz FCLK PRDCLK 1 FDIV 5 0 PRDCLK oscillator_clock PRDCLK oscillator_clock 8 PRDCLK MHz 5 Tbus ms no FDIV 5 0 PRDCLK MHz 5 Tbus ms 1 yes START Tbus 1ms an integer FDIV 5 0 INT PRDCLK MHz 5 Tbus ms 1 FCLK MHz Tbus ms 5 AND FCLK 0 15MHz END yes no FDIV 5 0 4 ALL COMMANDS IMPOSSIBLE yes no ALL COMMANDS IMPOSSIBLE no TRY TO DECREASE Tbus yes oscillator_clock ...

Page 523: ...steps However Flash register and array reads are allowed during a command write sequence The basic command write sequence is as follows 1 Write to a valid address in the Flash array memory 2 Write a valid command to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command The address written in step 1 will be stored in the FADDR registers and the...

Page 524: ...d is not allowed Table 18 16 Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased If the Flash array is erased the BLANK bit will set in the FSTAT register upon command completion 0x20 Program Program a word 2 bytes in the Flash array 0x40 Sector Erase Erase all 512 bytes in a sector of the Flash array 0x41 Mass Erase Erase all ...

Page 525: ... written will be ignored 2 Write the erase verify command 0x05 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command After launching the erase verify command the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered Upon completion of the erase verify op...

Page 526: ...x30 Write FSTAT register yes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CCIF Set ACCERR PVIOL Set no Erase Verify Status yes EXIT Flash Array Not Erased EXIT Flash Array Erased BLANK Set Write FCLKDIV register Read FCLKDIV registe...

Page 527: ...ogram command 0x20 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command If a word to be programmed is in a protected area of the Flash array the PVIOL flag in the FSTAT register will set and the program command will not launch Once the program command has successfully launched the CCIF flag in the FSTAT register will set after the ...

Page 528: ... no Access Error and Protection Violation no and program Data Bit Polling for Buffer Empty Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CBEIF Set ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset no yes Sequenti...

Page 529: ...the sector erase command The Flash address written determines the sector to be erased while MCU address bits 8 0 and the data written are ignored 2 Write the sector erase command 0x40 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command If a Flash sector to be erased is in a protected area of the Flash array the PVIOL flag in ...

Page 530: ...lear CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset...

Page 531: ...tart the command write sequence for the mass erase command The address and data written will be ignored 2 Write the mass erase command 0x41 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command If a Flash array to be erased contains any protected area the PVIOL flag in the FSTAT register will set and the mass erase command will n...

Page 532: ...ar CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset n...

Page 533: ...ding command is killed 10 When security is enabled a command other than mass erase originating from a non secure memory or from the background debug mode is written to the FCMD register 11 A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence The ACCERR flag will not be set if any Flash register is read during the command write sequence If the Flash array is read ...

Page 534: ...le 18 16 can be executed If the MCU is secured and is in special single chip mode the only possible command to execute is mass erase 18 4 3 Flash Module Security The Flash module provides the necessary security information to the MCU After each reset the Flash module determines the security state of the MCU as defined in Section 18 3 2 2 Flash Security Register FSEC The contents of the Flash secur...

Page 535: ...security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted The following illegal operations will lock the security state machine 1 If any of the four 16 bit words does not match the backdoor key programmed in the Flash array 2 If the four 16 bit words are written in the wrong sequence 3 If more than four 16 bit words are written 4 If any of the four ...

Page 536: ...s have completed execution or the Flash address data and command buffers are empty NOTE Vector addresses and their relative interrupt priority are determined at the MCU level 18 4 5 1 Description of Interrupt Operation Figure 18 26 shows the logic used for generating interrupts The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the ...

Page 537: ...se and sector erase An erased bit reads 1 and a programmed bit reads 0 The high voltage required to program and erase is generated internally It is not possible to read from a Flash array while it is being erased or programmed CAUTION A Flash word must be in the erased state before being programmed Cumulative programming of bits within a Flash word is not allowed 19 1 1 Glossary Command Write Sequ...

Page 538: ...rase operations refer to Section 19 4 1 Flash Command Operations 19 1 4 Block Diagram Figure 19 1Figure 19 2 shows a block diagram of the FTS128K1FTS64K module Figure 19 1 FTS128K1 Block Diagram FTS128K1 Oscillator Clock Command Complete Interrupt Command Buffer Empty Interrupt Flash Array 64K 16 Bits sector 0 sector 1 sector 127 Clock Divider FCLK Protection Security Command Pipeline cmd2 addr2 d...

Page 539: ...ule Memory Map The FTS128K1FTS64K memory map is shown in Figure 19 3Figure 19 4 The HCS12 architecture places the Flash array addresses between 0x40000x4000 and 0xFFFF which corresponds to three 16 Kbyte pages The content of the HCS12 Core PPAGE register is used to map the logical middle page ranging from FTS64K Oscillator Clock Command Complete Interrupt Command Buffer Empty Interrupt Flash Array...

Page 540: ...r code since it covers the vector space The lower address area can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field describ...

Page 541: ...0 0xFF0F Flash Configuration Field MODULE BASE 0x000F 0x8000 Flash Protected Low Sectors 1 2 4 8 Kbytes FLASH_START 0x4000 0x5000 0x4400 0x6000 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3E 0x3C 0x3D 003E 0x3F Note 0x38 0x3F correspond to the PPAGE register content FLASH_END 0xFFFF 0xF800 0xF000 0xC000 0xE000 Flash Protected High Sectors 2 4 8 16 Kbytes 0x3F 0x4800 Flash Array 16 bytes ...

Page 542: ...0000 0xFF00 0xFF0F Flash Configuration Field MODULE BASE 0x000F 0x8000 Flash Protected Low Sectors 1 2 4 8 Kbytes FLASH_START 0x4000 0x5000 0x4400 0x6000 16K PAGED MEMORY 0x3E 0x3C 0x3D 003E 0x3F Note 0x3C 0x3F correspond to the PPAGE register content FLASH_END 0xFFFF 0xF800 0xF000 0xC000 0xE000 Flash Protected High Sectors 2 4 8 16 Kbytes 0x3F 0x4800 Flash Array 16 bytes ...

Page 543: ...0 0x7FFF Unpaged 0x3E 0x4000 0x43FF N A 0x18000 0x1BFFF 0x4000 0x47FF 0x4000 0x4FFF 0x4000 0x5FFF 0x8000 0xBFFF 0x38 N A N A 0x00000 0x03FFF 0x39 N A N A 0x04000 0x07FFF 0x3A N A N A 0x08000 0x0BFFF 0x3B N A N A 0x0C000 0x0FFFF 0x3C N A N A 0x10000 0x13FFF 0x3D N A N A 0x14000 0x17FFF 0x3E 0x8000 0x83FF N A 0x18000 0x1BFFF 0x8000 0x87FF 0x8000 0x8FFF 0x8000 0x9FFF 0x3F N A 0xB800 0xBFFF 0x1C000 0x...

Page 544: ... allowed by MCU Unpaged 0x3D N A N A 0x14000 0x17FFF 0x4000 0x7FFF Unpaged 0x3E 0x4000 0x43FF N A 0x18000 0x1BFFF 0x4000 0x47FF 0x4000 0x4FFF 0x4000 0x5FFF 0x8000 0xBFFF 0x3C N A N A 0x10000 0x13FFF 0x3D N A N A 0x14000 0x17FFF 0x3E 0x8000 0x83FF N A 0x18000 0x1BFFF 0x8000 0x87FF 0x8000 0x8FFF 0x8000 0x9FFF 0x3F N A 0xB800 0xBFFF 0x1C000 0x1FFFF 0xB000 0xBFFF 0xA000 0xBFFF 0x8000 0xBFFF 0xC000 0xF...

Page 545: ...N0 NV5 NV4 NV3 NV2 SEC1 SEC0 W 0x0002 RESERVED1 1 1 Intended for factory test purposes only R 0 0 0 0 0 0 0 0 W 0x0003 FCNFG R CBEIE CCIE KEYACC 0 0 0 0 0 W 0x0004 FPROT R FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0005 FSTAT R CBEIF CCIF PVIOL ACCERR 0 BLANK FAIL DONE W 0x0006 FCMD R 0 CMDB6 CMDB5 0 0 CMDB2 0 CMDB0 W 0x0007 RESERVED21 R 0 0 0 0 0 0 0 0 W 0x0008 FADDRHI1 R FABHI W 0x0008...

Page 546: ... FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19 6 Flash Clock Divider Register FCLKDIV Table 19 4 FCLKDIV Field Descriptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset 6 PRDIV8 Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flash...

Page 547: ... 5 2 NV 5 2 Nonvolatile Flag Bits The NV 5 2 bits are available to the user as nonvolatile flags 1 0 SEC 1 0 Flash Security Bits The SEC 1 0 bits define the security state of the MCU as shown in Table 19 7 If the Flash module is unsecured using backdoor key access the SEC 1 0 bits are forced to 1 0 Table 19 6 Flash KEYEN States KEYEN 1 0 Status of Backdoor Key Access 00 DISABLED 01 1 1 Preferred K...

Page 548: ...eset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19 9 Flash Configuration Register FCNFG Table 19 8 FCNFG Field Descriptions Field Description 7 CBEIE Command Buffer Empty Interrupt Enable The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requested whenever the CBEIF flag is set see Sec...

Page 549: ...ange specified by the corresponding FPxS 1 0 bits When FPOPEN is cleared FPxDIS defines unprotected ranges as specified by the corresponding FPxS 1 0 bits In this case setting FPxDIS enables protection Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as shown in Table 19 10 This function allows the main part of the Flash array to be protected while a small range can rema...

Page 550: ...FPLS 0 Function 1 1 For range sizes refer to Table 19 11 and Table 19 12 or 1 1 x x 1 x x No protection 1 1 x x 0 x x Protect low range 1 0 x x 1 x x Protect high range 1 0 x x 0 x x Protect high and low ranges 0 1 x x 1 x x Full Flash array protected 0 0 x x 1 x x Unprotected high range 0 1 x x 0 x x Unprotected low range 0 0 x x 0 x x Unprotected high and low ranges Table 19 11 Flash Protection ...

Page 551: ... 13 Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged The contents of the FPROT register reflect the active protection scenario Table 19 13 Flash Protection Scenario Transitions From Protection Scenario To Protection Scenario 1 0 1 2 3 4 5 6 7 0 X X X X 1 X X 2 X X 3 X 4 X X 5 X X X X 7 6 5 4 FPOPEN 1 3 2 1 0 FPHS 1 0 FPLS 1...

Page 552: ...can be started The CBEIF flag is cleared by writing a 1 to CBEIF Writing a 0 to the CBEIF flag has no effect on CBEIF Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR f...

Page 553: ...sible to launch another command 0 No access error detected 1 Access error has occurred 2 BLANK Flash Array Has Been Verified as Erased The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence Writing to the BLANK flag has no effect on BLANK 0 ...

Page 554: ...iption 6 5 2 0 CMDB 6 5 CMDB 2 CMDB 0 Valid Flash commands are shown in Table 19 16 An attempt to execute any command other than those listed in Table 19 16 will set the ACCERR bit in the FSTAT register see Section 19 3 2 6 Table 19 16 Valid Flash Command List CMDB NVM Command 0x05 Erase verify 0x20 Word program 0x40 Sector erase 0x41 Mass erase Module Base 0x0007 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0...

Page 555: ...mal modes all FDATAHI and FDATALO bits read 0 and are not writable In special modes all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range Module Base 0x0008 7 6 5 4 3 2 1 0 R 0 FABHI W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19 16 Flash Address High Register FADDRHI Module Base 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 ...

Page 556: ... All bits read 0 and are not writable 19 3 2 13 RESERVED5 This register is reserved for factory testing and is not accessible to the user All bits read 0 and are not writable Module Base 0x000C 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19 20 RESERVED3 Module Base 0x000D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reser...

Page 557: ...ing more than one word on a specific row as the high voltage generation can be kept active in between two programming commands The pipelined operation also allows a simplification of command launching Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated if enabled The next sections describe How to write the FCLKDIV register...

Page 558: ...ON Because of the impact of clock synchronization on the accuracy of the functional timings programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz Programming or erasing the Flash array with an input clock 150 kHz should be avoided Setting FCLKDIV to a value such that FCLK 150 kHz can destroy the Flash array due to overstress Setting FCLKDIV to a value ...

Page 559: ...yes no PRDIV8 0 reset 12 8MHz FCLK PRDCLK 1 FDIV 5 0 PRDCLK oscillator_clock PRDCLK oscillator_clock 8 PRDCLK MHz 5 Tbus µs no FDIV 5 0 PRDCLK MHz 5 Tbus µs 1 yes START Tbus 1µs an integer FDIV 5 0 INT PRDCLK MHz 5 Tbus µs 1 FCLK MHz Tbus µs 5 AND FCLK 0 15MHz END yes no FDIV 5 0 4 ALL COMMANDS IMPOSSIBLE yes no ALL COMMANDS IMPOSSIBLE no TRY TO DECREASE Tbus yes oscillator_clock ...

Page 560: ...steps However Flash register and array reads are allowed during a command write sequence The basic command write sequence is as follows 1 Write to a valid address in the Flash array memory 2 Write a valid command to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command The address written in step 1 will be stored in the FADDR registers and the...

Page 561: ... is not allowed Table 19 17 Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased If the Flash array is erased the BLANK bit will set in the FSTAT register upon command completion 0x20 Program Program a word 2 bytes in the Flash array 0x40 Sector Erase Erase all 1024 bytes in a sector of the Flash array 0x41 Mass Erase Erase all ...

Page 562: ... written will be ignored 2 Write the erase verify command 0x05 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command After launching the erase verify command the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered Upon completion of the erase verify op...

Page 563: ...x30 Write FSTAT register yes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CCIF Set ACCERR PVIOL Set no Erase Verify Status yes EXIT Flash Array Not Erased EXIT Flash Array Erased BLANK Set Write FCLKDIV register Read FCLKDIV registe...

Page 564: ...ogram command 0x20 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command If a word to be programmed is in a protected area of the Flash array the PVIOL flag in the FSTAT register will set and the program command will not launch Once the program command has successfully launched the CCIF flag in the FSTAT register will set after the ...

Page 565: ... no Access Error and Protection Violation no and program Data Bit Polling for Buffer Empty Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CBEIF Set ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset no yes Sequenti...

Page 566: ...the sector erase command The Flash address written determines the sector to be erased while MCU address bits 9 0 and the data written are ignored 2 Write the sector erase command 0x40 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command If a Flash sector to be erased is in a protected area of the Flash array the PVIOL flag in ...

Page 567: ...lear CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset...

Page 568: ...tart the command write sequence for the mass erase command The address and data written will be ignored 2 Write the mass erase command 0x41 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command If a Flash array to be erased contains any protected area the PVIOL flag in the FSTAT register will set and the mass erase command will n...

Page 569: ...ar CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset n...

Page 570: ...ding command is killed 10 When security is enabled a command other than mass erase originating from a non secure memory or from the background debug mode is written to the FCMD register 11 A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence The ACCERR flag will not be set if any Flash register is read during the command write sequence If the Flash array is read ...

Page 571: ...le 19 17 can be executed If the MCU is secured and is in special single chip mode the only possible command to execute is mass erase 19 4 3 Flash Module Security The Flash module provides the necessary security information to the MCU After each reset the Flash module determines the security state of the MCU as defined in Section 19 3 2 2 Flash Security Register FSEC The contents of the Flash secur...

Page 572: ...security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted The following illegal operations will lock the security state machine 1 If any of the four 16 bit words does not match the backdoor key programmed in the Flash array 2 If the four 16 bit words are written in the wrong sequence 3 If more than four 16 bit words are written 4 If any of the four ...

Page 573: ...s have completed execution or the Flash address data and command buffers are empty NOTE Vector addresses and their relative interrupt priority are determined at the MCU level 19 4 5 1 Description of Interrupt Operation Figure 19 29 shows the logic used for generating interrupts The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the ...

Page 574: ...Chapter 19 64 Kbyte Flash Module S12FTS64KV4 574 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 575: ...se and sector erase An erased bit reads 1 and a programmed bit reads 0 The high voltage required to program and erase is generated internally It is not possible to read from a Flash array while it is being erased or programmed CAUTION A Flash word must be in the erased state before being programmed Cumulative programming of bits within a Flash word is not allowed 20 1 1 Glossary Command Write Sequ...

Page 576: ...rase operations refer to Section 20 4 1 Flash Command Operations 20 1 4 Block Diagram Figure 20 1Figure 20 2 shows a block diagram of the FTS128K1FTS96K module Figure 20 1 FTS128K1 Block Diagram FTS128K1 Oscillator Clock Command Complete Interrupt Command Buffer Empty Interrupt Flash Array 64K 16 Bits sector 0 sector 1 sector 127 Clock Divider FCLK Protection Security Command Pipeline cmd2 addr2 d...

Page 577: ...ule Memory Map The FTS128K1FTS96K memory map is shown in Figure 20 3Figure 20 4 The HCS12 architecture places the Flash array addresses between 0x40000x4000 and 0xFFFF which corresponds to three 16 Kbyte pages The content of the HCS12 Core PPAGE register is used to map the logical middle page ranging from FTS96K Oscillator Clock Command Complete Interrupt Command Buffer Empty Interrupt Flash Array...

Page 578: ...r code since it covers the vector space The lower address area can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected from program or erase Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field describ...

Page 579: ...0 0xFF0F Flash Configuration Field MODULE BASE 0x000F 0x8000 Flash Protected Low Sectors 1 2 4 8 Kbytes FLASH_START 0x4000 0x5000 0x4400 0x6000 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3E 0x3C 0x3D 003E 0x3F Note 0x38 0x3F correspond to the PPAGE register content FLASH_END 0xFFFF 0xF800 0xF000 0xC000 0xE000 Flash Protected High Sectors 2 4 8 16 Kbytes 0x3F 0x4800 Flash Array 16 bytes ...

Page 580: ...0xFF00 0xFF0F Flash Configuration Field MODULE BASE 0x000F 0x8000 Flash Protected Low Sectors 1 2 4 8 Kbytes FLASH_START 0x4000 0x5000 0x4400 0x6000 16K PAGED MEMORY 0x3A 0x3B 0x3E 0x3C 0x3D 003E 0x3F Note 0x3A 0x3F correspond to the PPAGE register content FLASH_END 0xFFFF 0xF800 0xF000 0xC000 0xE000 Flash Protected High Sectors 2 4 8 16 Kbytes 0x3F 0x4800 Flash Array 16 bytes ...

Page 581: ...0 0x7FFF Unpaged 0x3E 0x4000 0x43FF N A 0x18000 0x1BFFF 0x4000 0x47FF 0x4000 0x4FFF 0x4000 0x5FFF 0x8000 0xBFFF 0x38 N A N A 0x00000 0x03FFF 0x39 N A N A 0x04000 0x07FFF 0x3A N A N A 0x08000 0x0BFFF 0x3B N A N A 0x0C000 0x0FFFF 0x3C N A N A 0x10000 0x13FFF 0x3D N A N A 0x14000 0x17FFF 0x3E 0x8000 0x83FF N A 0x18000 0x1BFFF 0x8000 0x87FF 0x8000 0x8FFF 0x8000 0x9FFF 0x3F N A 0xB800 0xBFFF 0x1C000 0x...

Page 582: ...N A N A 0x14000 0x17FFF 0x4000 0x7FFF Unpaged 0x3E 0x4000 0x43FF N A 0x18000 0x1BFFF 0x4000 0x47FF 0x4000 0x4FFF 0x4000 0x5FFF 0x8000 0xBFFF 0x3A N A N A 0x08000 0x0BFFF 0x3B N A N A 0x0C000 0x0FFFF 0x3C N A N A 0x10000 0x13FFF 0x3D N A N A 0x14000 0x17FFF 0x3E 0x8000 0x83FF N A 0x18000 0x1BFFF 0x8000 0x87FF 0x8000 0x8FFF 0x8000 0x9FFF 0x3F N A 0xB800 0xBFFF 0x1C000 0x1FFFF 0xB000 0xBFFF 0xA000 0x...

Page 583: ... R KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 W 0x0002 RESERVED1 1 1 Intended for factory test purposes only R 0 0 0 0 0 0 0 0 W 0x0003 FCNFG R CBEIE CCIE KEYACC 0 0 0 0 0 W 0x0004 FPROT R FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0005 FSTAT R CBEIF CCIF PVIOL ACCERR 0 BLANK FAIL DONE W 0x0006 FCMD R 0 CMDB6 CMDB5 0 0 CMDB2 0 CMDB0 W 0x0007 RESERVED21 R 0 0 0 0 0 0 0 0 W 0x0008 FADDRHI1 R ...

Page 584: ... FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 20 6 Flash Clock Divider Register FCLKDIV Table 20 4 FCLKDIV Field Descriptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset 6 PRDIV8 Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flash...

Page 585: ... 5 2 NV 5 2 Nonvolatile Flag Bits The NV 5 2 bits are available to the user as nonvolatile flags 1 0 SEC 1 0 Flash Security Bits The SEC 1 0 bits define the security state of the MCU as shown in Table 20 7 If the Flash module is unsecured using backdoor key access the SEC 1 0 bits are forced to 1 0 Table 20 6 Flash KEYEN States KEYEN 1 0 Status of Backdoor Key Access 00 DISABLED 01 1 1 Preferred K...

Page 586: ...eset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 20 9 Flash Configuration Register FCNFG Table 20 8 FCNFG Field Descriptions Field Description 7 CBEIE Command Buffer Empty Interrupt Enable The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requested whenever the CBEIF flag is set see Sec...

Page 587: ...ange specified by the corresponding FPxS 1 0 bits When FPOPEN is cleared FPxDIS defines unprotected ranges as specified by the corresponding FPxS 1 0 bits In this case setting FPxDIS enables protection Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as shown in Table 20 10 This function allows the main part of the Flash array to be protected while a small range can rema...

Page 588: ...FPLS 0 Function 1 1 For range sizes refer to Table 20 11 and Table 20 12 or 1 1 x x 1 x x No protection 1 1 x x 0 x x Protect low range 1 0 x x 1 x x Protect high range 1 0 x x 0 x x Protect high and low ranges 0 1 x x 1 x x Full Flash array protected 0 0 x x 1 x x Unprotected high range 0 1 x x 0 x x Unprotected low range 0 0 x x 0 x x Unprotected high and low ranges Table 20 11 Flash Protection ...

Page 589: ... 13 Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged The contents of the FPROT register reflect the active protection scenario Table 20 13 Flash Protection Scenario Transitions From Protection Scenario To Protection Scenario 1 0 1 2 3 4 5 6 7 0 X X X X 1 X X 2 X X 3 X 4 X X 5 X X X X 7 6 5 4 FPOPEN 1 3 2 1 0 FPHS 1 0 FPLS 1...

Page 590: ...can be started The CBEIF flag is cleared by writing a 1 to CBEIF Writing a 0 to the CBEIF flag has no effect on CBEIF Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR f...

Page 591: ...sible to launch another command 0 No access error detected 1 Access error has occurred 2 BLANK Flash Array Has Been Verified as Erased The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence Writing to the BLANK flag has no effect on BLANK 0 ...

Page 592: ...iption 6 5 2 0 CMDB 6 5 CMDB 2 CMDB 0 Valid Flash commands are shown in Table 20 16 An attempt to execute any command other than those listed in Table 20 16 will set the ACCERR bit in the FSTAT register see Section 20 3 2 6 Table 20 16 Valid Flash Command List CMDB NVM Command 0x05 Erase verify 0x20 Word program 0x40 Sector erase 0x41 Mass erase Module Base 0x0007 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0...

Page 593: ... data registers In normal modes all FDATAHI and FDATALO bits read 0 and are not writable In special modes all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range 20 3 2 11 RESERVED3 This register is reserved for factory testing and is not accessible to the user Module Base 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 0 0 0 0 Figure 20 16 F...

Page 594: ...ing and is not accessible to the user All bits read 0 and are not writable 20 3 2 14 RESERVED6 This register is reserved for factory testing and is not accessible to the user Module Base 0x000C 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 20 19 RESERVED3 Module Base 0x000D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reser...

Page 595: ...etween two programming commands The pipelined operation also allows a simplification of command launching Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated if enabled The next sections describe How to write the FCLKDIV register Command write sequence used to program erase or erase verify the Flash array Valid Flash comma...

Page 596: ...tion on the accuracy of the functional timings programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz Programming or erasing the Flash array with an input clock 150 kHz should be avoided Setting FCLKDIV to a value such that FCLK 150 kHz can destroy the Flash array due to overstress Setting FCLKDIV to a value such that 1 FCLK Tbus 5µs can result in incom...

Page 597: ...yes no PRDIV8 0 reset 12 8MHz FCLK PRDCLK 1 FDIV 5 0 PRDCLK oscillator_clock PRDCLK oscillator_clock 8 PRDCLK MHz 5 Tbus µs no FDIV 5 0 PRDCLK MHz 5 Tbus µs 1 yes START Tbus 1µs an integer FDIV 5 0 INT PRDCLK MHz 5 Tbus µs 1 FCLK MHz Tbus µs 5 AND FCLK 0 15MHz END yes no FDIV 5 0 4 ALL COMMANDS IMPOSSIBLE yes no ALL COMMANDS IMPOSSIBLE no TRY TO DECREASE Tbus yes oscillator_clock ...

Page 598: ...steps However Flash register and array reads are allowed during a command write sequence The basic command write sequence is as follows 1 Write to a valid address in the Flash array memory 2 Write a valid command to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command The address written in step 1 will be stored in the FADDR registers and the...

Page 599: ... is not allowed Table 20 17 Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased If the Flash array is erased the BLANK bit will set in the FSTAT register upon command completion 0x20 Program Program a word 2 bytes in the Flash array 0x40 Sector Erase Erase all 1024 bytes in a sector of the Flash array 0x41 Mass Erase Erase all ...

Page 600: ... written will be ignored 2 Write the erase verify command 0x05 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command After launching the erase verify command the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered Upon completion of the erase verify op...

Page 601: ...x30 Write FSTAT register yes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CCIF Set ACCERR PVIOL Set no Erase Verify Status yes EXIT Flash Array Not Erased EXIT Flash Array Erased BLANK Set Write FCLKDIV register Read FCLKDIV registe...

Page 602: ...ogram command 0x20 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command If a word to be programmed is in a protected area of the Flash array the PVIOL flag in the FSTAT register will set and the program command will not launch Once the program command has successfully launched the CCIF flag in the FSTAT register will set after the ...

Page 603: ... no Access Error and Protection Violation no and program Data Bit Polling for Buffer Empty Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CBEIF Set ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset no yes Sequenti...

Page 604: ...the sector erase command The Flash address written determines the sector to be erased while MCU address bits 9 0 and the data written are ignored 2 Write the sector erase command 0x40 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command If a Flash sector to be erased is in a protected area of the Flash array the PVIOL flag in ...

Page 605: ...lear CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset...

Page 606: ...tart the command write sequence for the mass erase command The address and data written will be ignored 2 Write the mass erase command 0x41 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command If a Flash array to be erased contains any protected area the PVIOL flag in the FSTAT register will set and the mass erase command will n...

Page 607: ...ar CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset n...

Page 608: ...ding command is killed 10 When security is enabled a command other than mass erase originating from a non secure memory or from the background debug mode is written to the FCMD register 11 A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence The ACCERR flag will not be set if any Flash register is read during the command write sequence If the Flash array is read ...

Page 609: ...le 20 17 can be executed If the MCU is secured and is in special single chip mode the only possible command to execute is mass erase 20 4 3 Flash Module Security The Flash module provides the necessary security information to the MCU After each reset the Flash module determines the security state of the MCU as defined in Section 20 3 2 2 Flash Security Register FSEC The contents of the Flash secur...

Page 610: ...security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted The following illegal operations will lock the security state machine 1 If any of the four 16 bit words does not match the backdoor key programmed in the Flash array 2 If the four 16 bit words are written in the wrong sequence 3 If more than four 16 bit words are written 4 If any of the four ...

Page 611: ...s have completed execution or the Flash address data and command buffers are empty NOTE Vector addresses and their relative interrupt priority are determined at the MCU level 20 4 5 1 Description of Interrupt Operation Figure 20 28 shows the logic used for generating interrupts The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the ...

Page 612: ...Chapter 20 96 Kbyte Flash Module S12FTS96KV1 612 MC9S12C Family MC9S12GC Family Freescale Semiconductor Rev 01 24 ...

Page 613: ...and sector erase An erased bit reads 1 and a programmed bit reads 0 The high voltage required to program and erase is generated internally It is not possible to read from a Flash array while it is being erased or programmed CAUTION A Flash word must be in the erased state before being programmed Cumulative programming of bits within a Flash word is not allowed 21 1 1 Glossary Command Write Sequenc...

Page 614: ... 1 Flash Command Operations 21 1 4 Block Diagram Figure 21 1 shows a block diagram of the FTS128K1 module Figure 21 1 FTS128K1 Block Diagram 21 2 External Signal Description The FTS128K1 module contains no signals that connect off chip FTS128K1 Oscillator Clock Command Complete Interrupt Command Buffer Empty Interrupt Flash Array 64K 16 Bits sector 0 sector 1 sector 127 Clock Divider FCLK Protecti...

Page 615: ...ses can be activated for protection The Flash array addresses covered by these protectable regions are shown in Figure 21 2 The higher address area is mainly targeted to hold the boot loader code since it covers the vector space The lower address area can be used for EEPROM emulation in an MCU without an EEPROM module since it can be left unprotected while the remaining addresses are protected fro...

Page 616: ...F00 0xFF0F Flash Configuration Field MODULE BASE 0x000F 0x8000 Flash Protected Low Sectors 1 2 4 8 Kbytes FLASH_START 0x4000 0x5000 0x4400 0x6000 16K PAGED MEMORY 0x38 0x39 0x3A 0x3B 0x3E 0x3C 0x3D 003E 0x3F Note 0x38 0x3F correspond to the PPAGE register content FLASH_END 0xFFFF 0xF800 0xF000 0xC000 0xE000 Flash Protected High Sectors 2 4 8 16 Kbytes 0x3F 0x4800 Flash Array 16 bytes ...

Page 617: ...000 0x7FFF Unpaged 0x3E 0x4000 0x43FF N A 0x18000 0x1BFFF 0x4000 0x47FF 0x4000 0x4FFF 0x4000 0x5FFF 0x8000 0xBFFF 0x38 N A N A 0x00000 0x03FFF 0x39 N A N A 0x04000 0x07FFF 0x3A N A N A 0x08000 0x0BFFF 0x3B N A N A 0x0C000 0x0FFFF 0x3C N A N A 0x10000 0x13FFF 0x3D N A N A 0x14000 0x17FFF 0x3E 0x8000 0x83FF N A 0x18000 0x1BFFF 0x8000 0x87FF 0x8000 0x8FFF 0x8000 0x9FFF 0x3F N A 0xB800 0xBFFF 0x1C000 ...

Page 618: ...C R KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 W 0x0002 RESERVED1 1 1 Intended for factory test purposes only R 0 0 0 0 0 0 0 0 W 0x0003 FCNFG R CBEIE CCIE KEYACC 0 0 0 0 0 W 0x0004 FPROT R FPOPEN NV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0005 FSTAT R CBEIF CCIF PVIOL ACCERR 0 BLANK FAIL DONE W 0x0006 FCMD R 0 CMDB6 CMDB5 0 0 CMDB2 0 CMDB0 W 0x0007 RESERVED21 R 0 0 0 0 0 0 0 0 W 0x0008 FADDRHI1 R...

Page 619: ...5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 21 4 Flash Clock Divider Register FCLKDIV Table 21 3 FCLKDIV Field Descriptions Field Description 7 FDIVLD Clock Divider Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written to since the last reset 6 PRDIV8 Enable Prescalar by 8 0 The oscillator clock is directly fed into the Flas...

Page 620: ...5 5 2 NV 5 2 Nonvolatile Flag Bits The NV 5 2 bits are available to the user as nonvolatile flags 1 0 SEC 1 0 Flash Security Bits The SEC 1 0 bits define the security state of the MCU as shown in Table 21 6 If the Flash module is unsecured using backdoor key access the SEC 1 0 bits are forced to 1 0 Table 21 5 Flash KEYEN States KEYEN 1 0 Status of Backdoor Key Access 00 DISABLED 01 1 1 Preferred ...

Page 621: ... Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 21 7 Flash Configuration Register FCNFG Table 21 7 FCNFG Field Descriptions Field Description 7 CBEIE Command Buffer Empty Interrupt Enable The CBEIE bit enables the interrupts in case of an empty command buffer in the Flash module 0 Command Buffer Empty interrupts disabled 1 An interrupt will be requested whenever the CBEIF flag is set see S...

Page 622: ... range specified by the corresponding FPxS 1 0 bits When FPOPEN is cleared FPxDIS defines unprotected ranges as specified by the corresponding FPxS 1 0 bits In this case setting FPxDIS enables protection Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as shown in Table 21 9 This function allows the main part of the Flash array to be protected while a small range can rem...

Page 623: ...FPLS 0 Function 1 1 For range sizes refer to Table 21 10 and Table 21 11 or 1 1 x x 1 x x No protection 1 1 x x 0 x x Protect low range 1 0 x x 1 x x Protect high range 1 0 x x 0 x x Protect high and low ranges 0 1 x x 1 x x Full Flash array protected 0 0 x x 1 x x Unprotected high range 0 1 x x 0 x x Unprotected low range 0 0 x x 0 x x Unprotected high and low ranges Table 21 10 Flash Protection ...

Page 624: ...1 12 Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged The contents of the FPROT register reflect the active protection scenario Table 21 12 Flash Protection Scenario Transitions From Protection Scenario To Protection Scenario 1 0 1 2 3 4 5 6 7 0 X X X X 1 X X 2 X X 3 X 4 X X 5 X X X X 7 6 5 4 FPOPEN 1 3 2 1 0 FPHS 1 0 FPLS ...

Page 625: ... can be started The CBEIF flag is cleared by writing a 1 to CBEIF Writing a 0 to the CBEIF flag has no effect on CBEIF Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag in the FSTAT register to be set Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR ...

Page 626: ...ssible to launch another command 0 No access error detected 1 Access error has occurred 2 BLANK Flash Array Has Been Verified as Erased The BLANK flag indicates that an erase verify command has checked the Flash array and found it to be erased The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command write sequence Writing to the BLANK flag has no effect on BLANK 0...

Page 627: ...ription 6 5 2 0 CMDB 6 5 CMDB 2 CMDB 0 Valid Flash commands are shown in Table 21 15 An attempt to execute any command other than those listed in Table 21 15 will set the ACCERR bit in the FSTAT register see Section 21 3 2 6 Table 21 15 Valid Flash Command List CMDB NVM Command 0x05 Erase verify 0x20 Word program 0x40 Sector erase 0x41 Mass erase Module Base 0x0007 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 ...

Page 628: ...h data registers In normal modes all FDATAHI and FDATALO bits read 0 and are not writable In special modes all FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash address range 21 3 2 11 RESERVED3 This register is reserved for factory testing and is not accessible to the user Module Base 0x0009 7 6 5 4 3 2 1 0 R FABLO W Reset 0 0 0 0 0 0 0 0 Figure 21 14 ...

Page 629: ...ting and is not accessible to the user All bits read 0 and are not writable 21 3 2 14 RESERVED6 This register is reserved for factory testing and is not accessible to the user Module Base 0x000C 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 21 17 RESERVED3 Module Base 0x000D 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Rese...

Page 630: ...between two programming commands The pipelined operation also allows a simplification of command launching Buffer empty as well as command completion are signalled by flags in the FSTAT register with corresponding interrupts generated if enabled The next sections describe How to write the FCLKDIV register Command write sequence used to program erase or erase verify the Flash array Valid Flash comm...

Page 631: ...ation on the accuracy of the functional timings programming or erasing the Flash array cannot be performed if the bus clock runs at less than 1 MHz Programming or erasing the Flash array with an input clock 150 kHz should be avoided Setting FCLKDIV to a value such that FCLK 150 kHz can destroy the Flash array due to overstress Setting FCLKDIV to a value such that 1 FCLK Tbus 5µs can result in inco...

Page 632: ...1 yes no PRDIV8 0 reset 12 8MHz FCLK PRDCLK 1 FDIV 5 0 PRDCLK oscillator_clock PRDCLK oscillator_clock 8 PRDCLK MHz 5 Tbus µs no FDIV 5 0 PRDCLK MHz 5 Tbus µs 1 yes START Tbus 1µs an integer FDIV 5 0 INT PRDCLK MHz 5 Tbus µs 1 FCLK MHz Tbus µs 5 AND FCLK 0 15MHz END yes no FDIV 5 0 4 ALL COMMANDS IMPOSSIBLE yes no ALL COMMANDS IMPOSSIBLE no TRY TO DECREASE Tbus yes oscillator_clock ...

Page 633: ...e steps However Flash register and array reads are allowed during a command write sequence The basic command write sequence is as follows 1 Write to a valid address in the Flash array memory 2 Write a valid command to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command The address written in step 1 will be stored in the FADDR registers and t...

Page 634: ...rd is not allowed Table 21 16 Valid Flash Commands FCMD Meaning Function on Flash Array 0x05 Erase Verify Verify all bytes in the Flash array are erased If the Flash array is erased the BLANK bit will set in the FSTAT register upon command completion 0x20 Program Program a word 2 bytes in the Flash array 0x40 Sector Erase Erase all 1024 bytes in a sector of the Flash array 0x41 Mass Erase Erase al...

Page 635: ...a written will be ignored 2 Write the erase verify command 0x05 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify command After launching the erase verify command the CCIF flag in the FSTAT register will set after the operation has completed unless a new command write sequence has been buffered Upon completion of the erase verify o...

Page 636: ...0x30 Write FSTAT register yes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CCIF Set ACCERR PVIOL Set no Erase Verify Status yes EXIT Flash Array Not Erased EXIT Flash Array Erased BLANK Set Write FCLKDIV register Read FCLKDIV regist...

Page 637: ...rogram command 0x20 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the program command If a word to be programmed is in a protected area of the Flash array the PVIOL flag in the FSTAT register will set and the program command will not launch Once the program command has successfully launched the CCIF flag in the FSTAT register will set after the...

Page 638: ...es no Access Error and Protection Violation no and program Data Bit Polling for Buffer Empty Check Read FSTAT register yes Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check CBEIF Set ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset no yes Sequen...

Page 639: ...r the sector erase command The Flash address written determines the sector to be erased while MCU address bits 9 0 and the data written are ignored 2 Write the sector erase command 0x40 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the sector erase command If a Flash sector to be erased is in a protected area of the Flash array the PVIOL flag i...

Page 640: ... Clear CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each res...

Page 641: ...start the command write sequence for the mass erase command The address and data written will be ignored 2 Write the mass erase command 0x41 to the FCMD register 3 Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the mass erase command If a Flash array to be erased contains any protected area the PVIOL flag in the FSTAT register will set and the mass erase command will ...

Page 642: ...ear CBEIF 0x80 1 2 3 Clear ACCERR PVIOL 0x30 Write FSTAT register yes no Access Error and Protection Violation and Dummy Data Read FSTAT register Read FSTAT register no START yes Check CBEIF Set Address Data Command Buffer Empty Check ACCERR PVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set NOTE FCLKDIV needs to be set once after each reset ...

Page 643: ...nding command is killed 10 When security is enabled a command other than mass erase originating from a non secure memory or from the background debug mode is written to the FCMD register 11 A 0 is written to the CBEIF bit in the FSTAT register to abort a command write sequence The ACCERR flag will not be set if any Flash register is read during the command write sequence If the Flash array is read...

Page 644: ...ble 21 16 can be executed If the MCU is secured and is in special single chip mode the only possible command to execute is mass erase 21 4 3 Flash Module Security The Flash module provides the necessary security information to the MCU After each reset the Flash module determines the security state of the MCU as defined in Section 21 3 2 2 Flash Security Register FSEC The contents of the Flash secu...

Page 645: ...e security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted The following illegal operations will lock the security state machine 1 If any of the four 16 bit words does not match the backdoor key programmed in the Flash array 2 If the four 16 bit words are written in the wrong sequence 3 If more than four 16 bit words are written 4 If any of the fou...

Page 646: ...ds have completed execution or the Flash address data and command buffers are empty NOTE Vector addresses and their relative interrupt priority are determined at the MCU level 21 4 5 1 Description of Interrupt Operation Figure 21 26 shows the logic used for generating interrupts The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to discriminate for the...

Page 647: ...e electrical parameters shown in this supplement are guaranteed by various methods To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification will be added at a later release of the specification P Those parameters are guaranteed during production testing on each individual devi...

Page 648: ...o VDD1 and VDD2 A 1 3 Pins There are four groups of functional pins A 1 3 1 5V I O Pins Those I O pins have a nominal level of 5V This class of pins is comprised of all port I O pins the analog inputs BKGD pin and the RESET inputs The internal structure of all those pins is identical however some of the functionality may be disabled For example pull up and pull down resistors may be disabled perma...

Page 649: ...A 1 Absolute Maximum Ratings Num Rating Symbol Min Max Unit 1 I O Regulator and Analog Supply Voltage VDD5 0 3 6 5 V 2 Digital Logic Supply Voltage 1 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when the device is powered from an external source VDD 0 3 3 0 V 3 PLL Supply Voltage 1 VDDPLL 0 3 3 0 V...

Page 650: ...ecification at room temperature followed by hot temperature unless specified otherwise in the device specification Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Human Body Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Number of Pulse per pin Positive Negative 3 3 Machine Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Number of Pulse per pin Po...

Page 651: ... Voltage 1 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The operating conditions apply when this regulator is disabled and the device is powered from an external source Using an external regulator with the internal voltage regulator disabled an external LVR must be provided VDD 2 35 2 5 2 75 V PLL Supply Voltage 1 VDDPLL 2 35 2 5 2 ...

Page 652: ... currents on I O ports associated with VDDX and VDDM For RDSON is valid respectively 2 Internal voltage regulator enabled IDDR is the current shown in Table A 8 and not the overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high Which is the sum of all output currents on I O ports associated with VDDX and VDDR T J T A P D Θ JA T J ...

Page 653: ...θJA 53 o C W 3 T Junction to Board LQFP48 θJB 30 o C W 4 T Junction to Case LQFP48 θJC 20 o C W 5 T Junction to Package Top LQFP48 ΨJT 4 o C W 6 T Thermal Resistance LQFP52 single sided PCB θJA 65 o C W 7 T Thermal Resistance LQFP52 double sided PCB with 2 internal planes θJA 49 o C W 8 T Junction to Board LQFP52 θJB 31 o C W 9 T Junction to Case LQFP52 θJC 17 o C W 10 T Junction to Package Top LQ...

Page 654: ...to 12 C in the temper ature range from 50 C to 125 C I in 1 µA 5 C Output High Voltage pins in output mode Partial Drive IOH 2mA V OH VDD5 0 8 V 6 P Output High Voltage pins in output mode Full Drive IOH 10mA VOH VDD5 0 8 V 7 C Output Low Voltage pins in output mode Partial Drive IOL 2mA VOL 0 8 V 8 P Output Low Voltage pins in output mode Full Drive IOL 10mA V OL 0 8 V 9 P Internal Pull Up Device...

Page 655: ...t occurs at maximum operating temperature Current decreases by approximately one half for each 8 C to 12 C in the temper ature range from 50 C to 125 C I in 1 1 µA 5 C Output High Voltage pins in output mode Partial Drive IOH 0 75mA V OH VDD5 0 4 V 6 P Output High Voltage pins in output mode Full Drive IOH 4mA V OH VDD5 0 4 V 7 C Output Low Voltage pins in output mode Partial Drive IOL 0 9mA V OL ...

Page 656: ...DDR 4 9V only RTI enabled2 VDDR 4 9V only RTI enabled IDDW 3 5 2 5 30 8 mA 3 C P C P C P C P Pseudo Stop Current RTI and COP disabled 2 3 40 C 27 C 85 C C Temp Option 100 C 105 C V Temp Option 120 C 125 C M Temp Option 140 C IDDPS 1 1 STOP current measured in production test at increased junction temperature hence for Temp Option C the test is carried out at 100 C although the Temperature specific...

Page 657: ...5 C V Temp Option 120 C 125 C M Temp Option 140 C IDDPS 1 1 STOP current measured in production test at increased junction temperature hence for Temp Option C the test is carried out at 100 C although the Temperature specification is 85 C Similarly for v and M options the temperature used in test lies 15 C above the temperature option specification 190 200 300 400 450 600 650 1000 250 1400 1900 48...

Page 658: ... beyond the power supply levels that it ties to If the input level goes outside of this range it will effectively be clipped Table A 10 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Supply Voltage 5V 10 VDDA 5V 10 Num C Rating Symbol Min Typ Max Unit 1 D Reference Potential Low High VRL VRH VSSA VDDA 2 VDDA 2 VDDA V V 2 C Differential Reference Voltage 1 1 ...

Page 659: ...less than worst case or leakage induced error is acceptable larger values of source resistance is allowable A 2 3 2 Source Capacitance When sampling an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage 1LSB then the external filter capacitor Cf 1024 C...

Page 660: ... any errors due to current injection input capacitance and source resistance Table 21 18 ATD Electrical Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 C Max input Source Resistance RS 1 KΩ 2 T Total Input Capacitance Non Sampling Sampling CINN CINS 10 15 pF 3 C Disruptive Analog Input Current INA 2 5 2 5 mA 4 C Coupling Ratio positiv...

Page 661: ...e Conditions are shown in Table A 4 unless otherwise noted VREF VRH VRL 3 328V Resulting to one 8 bit count 13mV and one 10 bit count 3 25mV fATDCLK 2 0MHz Num C Rating Symbol Min Typ Max Unit 1 P 10 Bit Resolution LSB 3 25 mV 2 P 10 Bit Differential Nonlinearity DNL 1 5 1 5 Counts 3 P 10 Bit Integral Nonlinearity INL 3 5 1 5 3 5 Counts 4 P 10 Bit Absolute Error 1 1 These values include the quanti...

Page 662: ...ues refer to Table A 12 1 3 25 Vin mV 6 5 9 75 13 16 25 19 5 22 75 26 3305 3309 3312 3315 3318 3321 3324 3328 3292 3295 3299 3302 3289 0 3 2 5 4 7 6 29 25 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit Resolution Ideal Transfer Curve 10 Bit Transfer Curve 8 Bit Transfer Curve 3286 10 Bit Absolute Error Boundary 8 Bit Absolute Error Boundary LSB Vi 1 Vi...

Page 663: ...s given by nuposc A 4 1 2 LVR The release level VLVRR and the assert level VLVRA are derived from the VDD supply They are also valid if the device is powered externally After releasing the LVR reset the oscillator and the clock quality check are started If after a time tCQOUT no valid oscillation is detected the MCU will start using the internal self clock The fastest startup time possible is give...

Page 664: ... in both modes In Pseudo Stop Mode the voltage regulator is switched to reduced performance mode to reduce power consumption The returning out of pseudo stop to full performance takes tvup The controller can be woken up by internal or external interrupts After twrs in Wait or tvup twrs in Pseudo Stop the CPU starts fetching the interrupt vector A 4 2 Oscillator The device features an internal Colp...

Page 665: ...time out tCQOUT 0 45 2 5 s 5 P Clock Monitor Failure Assert Frequency fCMFA 50 100 200 KHz 6 P External square wave input frequency 4 4 Only valid if Pierce Oscillator external clock selected XCLKS 0 during reset fEXT 0 5 50 MHz 7 D External square wave pulse width low tEXTL 9 5 ns 8 D External square wave pulse width high tEXTH 9 5 ns 9 D External square wave rise time tEXTR 1 ns 10 D External sq...

Page 666: ...A 2 Basic PLL Functional Diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1 f1 and ich from Table A 17 The grey boxes show the calculation for fVCO 50MHz and fref 1MHz E g these frequencies are used for fOSC 4MHz and a 25MHz bus clock The VCO Gain at the desired VCO frequency is approximated by The phase detector relationship ...

Page 667: ...e of A 4 3 2 Jitter Information The basic functionality of the PLL is shown in Figure A 3 With each transition of the clock fcmp the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in th...

Page 668: ...or larger number of clock periods N Defining the jitter as For N 100 the following equation is a good fit for the maximum jitter Figure A 4 Maximum Bus Clock Jitter Approximation This is very important to notice with respect to timers serial modules where a pre scaler will eliminate the effect of the jitter to a large extent 2 3 N 1 N 1 0 tnom tmax1 tmin1 tmaxN tminN J N max 1 tmax N N tnom 1 tmin...

Page 669: ...r maximum fNVMOP and maximum fbus The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz Table A 17 PLL Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Self Clock Mode frequency fSCM 1 5 5 MHz 2 D VCO locking range fVCO 8 50 MHz 3 D Lock Detector transition from Acquisition to Tracking mode trk 3 4 1 1 deviation from...

Page 670: ...ng the command pipeline filled the time to program a whole row is For the C64 GC64 C96 C128 and GC128 device flash arrays where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled the time to program a whole row is Row programming is more than 2 times faster than single word programming A 5 1 3 Sector Erase Erasing either a 512 byte or 1024 byte Flash sec...

Page 671: ...requency f bus Refer to formulae in Sections A 3 1 1 A 3 1 4 for guidance µs 5 D Flash Burst Programming consecutive word tbwpgm 20 42 313 µs 6 D Flash Burst Programming Time for 32 Word row tbrpgm 678 42 1035 53 µs 6 D Flash Burst Programming Time for 64 Word row tbrpgm 1331 22 2027 53 µs 7 P Sector Erase Time tera 20 4 4 Minimum Erase times are achieved under maximum NVM operating frequency f NV...

Page 672: ...C Data retention after 10 000 program erase cycles at an average junction temperature of TJavg 85 C tFLRET 15 100 2 2 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de rated to 25 C using the Arrhenius equation For additional information on how Freescale defines Typical Data Retention please refer to Engineering Bulletin EB618 Yea...

Page 673: ...ment conditions are listed A 6 1 Master Mode In Figure A 6 the timing diagram for master mode with transmission format CPHA 0 is depicted Table A 20 Measurement Conditions Description Value Unit Drive mode Full drive mode Load capacitance CLOAD on all outputs 50 pF Thresholds for delay measurement points 20 80 VDDX V Typical Endurance 10 3 Cycles Operating Temperature TJ C 0 50 100 150 200 250 300...

Page 674: ...SCK OUTPUT MISO INPUT MOSI OUTPUT SS1 OUTPUT 1 9 5 6 MSB IN2 BIT 6 1 LSB IN MSB OUT2 LSB OUT BIT 6 1 11 4 4 2 10 CPOL 0 CPOL 1 3 13 13 1 If configured as an output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB 12 12 SCK OUTPUT SCK OUTPUT MISO INPUT MOSI OUTPUT 1 5 6 MSB IN2 BIT 6 1 LSB IN MASTER MSB OUT2 MASTER LSB OUT BIT 6 1 4 4 9 12 13 11 PORT DATA CPOL 0 CPOL 1 PORT DATA SS1 OUTPUT 2 12...

Page 675: ... 2048 1 2 fbus 1 P SCK Period tsck 2 2048 tbus 2 D Enable Lead Time tlead 1 2 tsck 3 D Enable Lag Time tlag 1 2 tsck 4 D Clock SCK High or Low Time twsck 1 2 tsck 5 D Data Setup Time Inputs tsu 8 ns 6 D Data Hold Time Inputs thi 8 ns 9 D Data Valid after SCK Edge tvsck 30 ns 10 D Data Valid after SS fall CPHA 0 tvss 15 ns 11 D Data Hold Time Outputs tho 20 ns 12 D Rise and Fall Time Inputs trfi 8 ...

Page 676: ... 3 D Enable Lag Time tlag 4 tbus 4 D Clock SCK High or Low Time twsck 4 tbus 5 D Data Setup Time Inputs tsu 8 ns 6 D Data Hold Time Inputs thi 8 ns 7 D Slave Access Time time to data active ta 20 ns 8 D Slave MISO Disable Time tdis 22 ns 9 D Data Valid after SCK Edge tvsck 30 tbus 1 1 tbus added due to internal synchronization delay ns 10 D Data Valid after SS fall tvss 30 tbus 1 ns 11 D Data Hold...

Page 677: ...rmance Mode VDD 2 35 2 5 2 75 V 4 P Low Voltage Interrupt 1 Assert Level xL45J mask set Assert Level other mask sets Deassert Level xL45J mask set Deassert Level other mask sets 1 Monitors VDDA active only in Full Performance Mode Indicates I O ADC performance degradation due to low supply voltage VLVIA VLVIA VLVID VLVID 4 30 4 00 4 42 4 15 4 53 4 37 4 65 4 52 4 77 4 66 4 89 4 77 V V V V 5 P Low V...

Page 678: ...al logic and oscillator circuits allows no external DC loads A 7 3 2 Capacitive Loads The capacitive loads are specified in Table A 24 Ceramic capacitors with X7R dielectricum are required Table A 24 Voltage Regulator Capacitive Loads Num Characteristic Symbol Min Typical Max Unit 1 VDD external capacitive load CDDext 400 440 12000 nF 2 VDDPLL external capacitive load CDDPLLext 90 220 5000 nF VLVI...

Page 679: ...SS PM4 MOSI PM5 SCK PJ6 KWJ6 PJ7 KWJ7 NC NC PP6 KWP6 ROMONE NC NC PS3 PS2 PS1 TXD PS0 RXD NC NC VSSA VRL PW3 KWP3 PP3 PW2 KWP2 PP2 PW1 KWP1 PP1 PW0 KWP0 PP0 NC XADDR16 PK2 XADDR15 PK1 XADDR14 PK0 IOC0 PT0 IOC1 PT1 IOC2 PT2 IOC3 PT3 VDD1 VSS1 IOC4 PT4 IOC5 PT5 IOC6 PT6 IOC7 PT7 NC NC NC NC MODC TAGHI BKGD ADDR0 DATA0 PB0 ADDR1 DATA1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 ADDR5 DATA5 PB...

Page 680: ...tate of DDRK in the S12_CORE is 00 configuring the pins as inputs The reset state of PUPKE in the PUCR register of the S12_CORE is 1 enabling the internal pullup resistors at PortK 2 0 In this reset state the pull up resistors provide a defined state and prevent a floating input thereby preventing unnecessary current consumption at the input stage Pin Name Function 1 Pin Name Function 2 Power Doma...

Page 681: ...Package Information Freescale Semiconductor MC9S12C Family MC9S12GC Family 681 Rev 01 24 Appendix C Package Information C 1 General This section provides the physical dimensions of the packages 48LQFP 52LQFP 80QFP ...

Page 682: ... INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT SECTION B B 61 60 DETAIL A L 41 40 80 A L D A S A B M 0 20 D S H 0 05 A B S 1 20 21 B B V J F N D VIEW ROTATED 90 DETAIL A B B P...

Page 683: ... EXCEED 0 46 0 018 MINIMUMSPACEBETWEENPROTRUSIONANDADJACENTLEAD OR PROTRUSION 0 07 0 003 VIEW AA AB AB VIEW Y SECTION AB AB ROTATED 90 CLOCKWISE DIM A MIN MAX MIN MAX INCHES 10 00 BSC 0 394 BSC MILLIMETERS A1 5 00 BSC 0 197 BSC B 10 00 BSC 0 394 BSC B1 5 00 BSC 0 197 BSC C 1 70 0 067 C1 0 05 0 20 0 002 0 008 C2 1 30 1 50 0 051 0 059 D 0 20 0 40 0 008 0 016 E 0 45 0 030 F 0 22 0 35 0 009 0 014 G 0 ...

Page 684: ...THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE 4 DATUMS T U AND Z TO BE DETERMINED AT DATUM PLANE AB 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 250 PER SIDE DIMENSIONS AANDBDOINCLUDEMOLDMISMATCHAND ARE DETERMINED AT DATUM PLANE AB 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR P...

Page 685: ...he C family that do not feature a CAN module Table D 1 shows a feature overview of the C and GC family members Table D 1 List of MC9S12C and MC9S12GC Family members 1 1 All family memebers are available in 80QFP 52LQFP and 48LQFP package options Flash RAM Device CAN SCI SPI A D PWM Timer 128K 4K MC9S12C128 1 1 1 8ch 6ch 8ch MC9S12GC128 1 1 8ch 6ch 8ch 96K 4K MC9S12C96 1 1 1 8ch 6ch 8ch MC9S12GC96 ...

Page 686: ...MPB XL09S 0M66G 40 C 125 C 52LQFP 25MHz C128 die 128K 4K 35 MC9S12C128MFU XL09S 0M66G 40 C 125 C 80QFP 25MHz C128 die 128K 4K 60 MC9S12C96CFA XL09S 0M66G 40 C 85 C 48LQFP 25MHz C128 die 96K 4K 31 MC9S12C96CPB XL09S 0M66G 40 C 85 C 52LQFP 25MHz C128 die 96K 4K 35 MC9S12C96CFU XL09S 0M66G 40 C 85 C 80QFP 25MHz C128 die 96K 4K 60 MC9S12C96VFA XL09S 0M66G 40 C 105 C 48LQFP 25MHz C128 die 96K 4K 31 MC9...

Page 687: ...2C32CFU25 xL45J xM34C 40 C 85 C 80QFP 25MHz C32 die 32K 2K 60 MC9S12C32VFA25 xL45J xM34C 40 C 105 C 48LQFP 25MHz C32 die 32K 2K 31 MC9S12C32VPB25 xL45J xM34C 40 C 105 C 52LQFP 25MHz C32 die 32K 2K 35 MC9S12C32VFU25 xL45J xM34C 40 C 105 C 80QFP 25MHz C32 die 32K 2K 60 MC9S12C32MFA25 xL45J xM34C 40 C 125 C 48LQFP 25MHz C32 die 32K 2K 31 MC9S12C32MPB25 xL45J xM34C 40 C 125 C 52LQFP 25MHz C32 die 32K ...

Page 688: ... 105 C 80QFP 25MHz C32 die 16K 1K 60 MC9S12GC16MFA xL45J xM34C 40 C 125 C 48LQFP 25MHz C32 die 16K 1K 31 MC9S12GC16MPB xL45J xM34C 40 C 125 C 52LQFP 25MHz C32 die 16K 1K 35 MC9S12GC16MFU xL45J xM34C 40 C 125 C 80QFP 25MHz C32 die 16K 1K 60 1 XL09S denotes all minor revisions of L09S maskset XL45J denotes all minor revisions of L45J maskset Maskset dependent errata can be accessed at http e www mot...

Page 689: ......

Page 690: ...ctor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Frees...

Page 691: ...9S12C64CFAER MC9S12C64CFUE MC9S12C64CPBE MC9S12C64VFAE MC9S12C64VFUE MC9S12C96CFAE MC9S12C96VPBE MC9S12GC128CFUE MC9S12GC16CFAE MC9S12GC16CFUE MC9S12GC16CPBE MC9S12GC16MFUE MC9S12GC32CFAE MC9S12GC32CFUE MC9S12GC32CPBE MC9S12GC32MFUE MC9S12GC32MPBE MC9S12GC32VFAE MC9S12GC64CFAE MC9S12GC64CFUE MC9S12GC96CFAE MC9S12GC96CFUE MCS12GC64CFUE NXP S9S12C128J2VFAER MC9S12C128MFAE MC9S12C64MFAE MC9S12C96MFUE...

Reviews:

No comments

Related manuals for MC9S12C Family

Balboa Instruments EL Series Hot Sheet preview
EL Series
Brand: Balboa Instruments Pages: 10
UCS CAT Quick Start Manual preview
CAT
Brand: UCS Pages: 4
Reer MOSAIC MA2 Quick Installation Manual preview
MOSAIC MA2
Brand: Reer Pages: 2
CORNING Ascent 6970 Instruction Manual preview
Ascent 6970
Brand: CORNING Pages: 142
Vimar by-me Eikon 20526 Quick Start Manual preview
by-me Eikon 20526
Brand: Vimar Pages: 6
Eaton DCF 800 TWIN Installation And Maintenance preview
DCF 800 TWIN
Brand: Eaton Pages: 2
Instrutech VGC301 User Manual preview
VGC301
Brand: Instrutech Pages: 42
LS Industrial Systems GLOFA G7M-DR20U User Manual preview
GLOFA G7M-DR20U
Brand: LS Industrial Systems Pages: 367
Belimo GM24A-MOD Technical Data Sheet preview
GM24A-MOD
Brand: Belimo Pages: 6
Linear Technology LTC4232 Demo Manual preview
LTC4232
Brand: Linear Technology Pages: 6
TA DA 516 Manual preview
DA 516
Brand: TA Pages: 8
UCS NANO DC Manual preview
NANO DC
Brand: UCS Pages: 44
EtherCAT TMCL Firmware Manual preview
TMCL
Brand: EtherCAT Pages: 107
PR Lighting NOVA PR-2013D Manual preview
NOVA PR-2013D
Brand: PR Lighting Pages: 12
YOKOGAWA AQ2201 User Manual preview
AQ2201
Brand: YOKOGAWA Pages: 3
VisAccess VXS-5 Installation Instructions preview
VXS-5
Brand: VisAccess Pages: 3
Mitsubishi AL2-2TC-ADP Installation Manual preview
AL2-2TC-ADP
Brand: Mitsubishi Pages: 2
Texmate Leopard Series Manual preview
Leopard Series
Brand: Texmate Pages: 10

Brands by name

Popular brands

Load more brands