Chapter 19 64 Kbyte Flash Module (S12FTS64KV4)
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
555
Rev 01.24
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In normal modes, all FABHI and FABLO bits read 0 and are not writable. In special modes, the FABHI
and FABLO bits are readable and writable. For sector erase, the MCU address bits
[9:0] are ignored
. For
mass erase, any address within the Flash array is valid to start the command.
19.3.2.10 Flash Data Register (FDATA)
FDATAHI and FDATALO are the Flash data registers.
In normal modes, all FDATAHI and FDATALO bits read 0 and are not writable. In special modes, all
FDATAHI and FDATALO bits are readable and writable when writing to an address within the Flash
address range.
Module Base + 0x0008
7
6
5
4
3
2
1
0
R
0
FABHI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-16. Flash Address High Register (FADDRHI)
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
FABLO
W
Reset
0
0
0
0
0
0
0
0
Figure 19-17. Flash Address Low Register (FADDRLO)
Module Base + 0x000A
7
6
5
4
3
2
1
0
R
FDHI
W
Reset
0
0
0
0
0
0
0
0
Figure 19-18. Flash Data High Register (FDATAHI)
Module Base + 0x000B
7
6
5
4
3
2
1
0
R
FDLO
W
Reset
0
0
0
0
0
0
0
0
Figure 19-19. Flash Data Low Register (FDATALO)
Summary of Contents for MC9S12C Family
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