Appendix A Electrical Characteristics
666
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24
A.4.3
Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
A.4.3.1
XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Figure A-2. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K
1
, f
1
and i
ch
from
.
The grey boxes show the calculation for f
VCO
= 50MHz and f
ref
= 1MHz. E.g., these frequencies are used
for f
OSC
= 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
The phase detector relationship is given by:
i
ch
is the current in tracking mode.
f
osc
1
refdv+1
f
ref
Phase
Detector
VCO
KV
1
synr+1
f
vco
Loop Divider
KF
1
2
D
f
cmp
Cs
R
Cp
V
DDPLL
XFC Pin
K
V
K
1
e
f
1
f
vco
–
(
)
K
1
1V
⋅
-----------------------
⋅
=
100
–
e
60 50
–
(
)
100
–
----------------------
⋅
=
= -90.48MHz/V
K
Φ
i
ch
–
K
V
⋅
=
=
316.7Hz/
Ω
Summary of Contents for MC9S12C Family
Page 689: ......
