Chapter 21 128 Kbyte Flash Module (S12FTS128K1V1)
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
619
Rev 01.24
21.3.2.1
Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
21.3.2.2
Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
All bits in the FSEC register are readable but not writable.
The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence,
indicated by F in
.
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
FDIVLD
PRDIV8
FDIV5
FDIV4
FDIV3
FDIV2
FDIV1
FDIV0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-4. Flash Clock Divider Register (FCLKDIV)
Table 21-3. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written to since the last reset
6
PRDIV8
Enable Prescalar by 8
0 The oscillator clock is directly fed into the Flash clock divider
1 The oscillator clock is divided by 8 before feeding into the Flash clock divider
5–0
FDIV[5:0]
Clock Divider Bits
— The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to
Section 21.4.1.1, “Writing the
for more information.
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
KEYEN1
KEYEN0
NV5
NV4
NV3
NV2
SEC1
SEC0
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 21-5. Flash Security Register (FSEC)
Summary of Contents for MC9S12C Family
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