Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
102
Freescale Semiconductor
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTS or PTIS registers, when changing the
DDRS register.
2.3.25
PIM Reserved Registers
3
DDRS
Port S data direction—
This register controls the data direction of pin 3.This register configures pin as either input or output.
If CAN is enabled, it will force the pin as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
2
DDRS
Port S data direction—
This register controls the data direction of pin 2.This register configures pin as either input or output.
If CAN is enabled, it will force the pin as input.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
1
DDRS
Port S data direction—
This register controls the data direction of pin 1.This register configures pin as either input or output.
If SCI is enabled, it will force the pin as output
Else if PWM7 is routing to PS1 and use as PWM channel output, it will force pin as output. If use as PWM emergency
shut down, it will force pin as input.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0
DDRS
Port S data direction—
This register controls the data direction of pin 0.This register configures pin as either input or output.
If SCI is enabled, it will force the pin as input
Else if PWM6 is routing to PS0 and PWM6 is enabled, it will force pin as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Address 0x024B
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-23. PIM Reserved Register)
Table 2-19. DDRS Register Field Descriptions (continued)
Field
Description
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