Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
111
2.3.38
PIM Reserved Register
2.3.39
Port P Data Register (PTP)
Address 0x0257
Access: User read
1
1
Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-35. PIM Reserved Register
Address 0x0258
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
W
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Altern.
Function
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
Reset
0
0
0
0
0
0
0
0
Figure 2-36. Port P Data Register (PTP)
Table 2-31. PTP Register Field Descriptions
Field
Description
7-0
PTP
Port P general purpose input/output data—Data Register, LCD segment driver output, PWM channel output
Port P pins are associated with the PWM channel output and LCD segment driver output.
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
• The LCD segment takes precedence over the PWM function and the general purpose I/O function is LCD
segment output is enabled
• The PWM function takes precedence over the general purpose I/O function if the PWM channel is enabled.
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