Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
113
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
2.3.42
PIM Reserved Registers
2.3.43
Port P Pull Device Enable Register (PERP)
Table 2-33. DDRP Register Field Descriptions
Field
Description
7
DDRP
Port P data direction—
This register controls the data direction of pin 7.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this
pin is forced to be an input. In these cases the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
6-0
DDRP
Port P data direction—
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel.
In this case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Address 0x025B
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-39. PIM Reserved Register
Address 0x025C
Access: User read/write
1
7
6
5
4
3
2
1
0
R
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
W
Reset
1
1
1
1
1
1
1
1
Figure 2-40. Port P Pull Device Enable Register (PERP)
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