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Port Integration Module (S12XHYPIMV1)

MC9S12XHY-Family Reference Manual, Rev. 1.01

Freescale Semiconductor

119

NOTE

Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.

Table 2-41. DDRH Register Field Descriptions

Field

Description

7-4

DDRH

Port H data direction—
This register controls the data direction of pin 7-4.
If enabled the LCD segment output it will force the I/O state to be a input/output diabled.

1 Associated pin is configured as output.
0 Associated pin is configured as input.

3

DDRH

Port H data direction—
This register controls the data direction of pin 3.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled

Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction

1 Associated pin is configured as output.
0 Associated pin is configured as input.

2

DDRH

Port H data direction—
This register controls the data direction of pin 2.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction
Else if ECLK is enabled, it will force the pin to output.

1 Associated pin is configured as output.
0 Associated pin is configured as input.

1

DDRH

Port H data direction—
This register controls the data direction of pin 1.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the SCI1 is routing to PH and SCI1 is enabled, the SCI1 will determined the pin direction
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction.

1 Associated pin is configured as output.
0 Associated pin is configured as input.

0

DDRH

Port H data direction—
This register controls the data direction of pin 0.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled

Else if the SCI1 is routing to PH and SCI1 is enabled, the SCI1 will determined the pin direction
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction t.

1 Associated pin is configured as output.
0 Associated pin is configured as input.

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Summary of Contents for MC9S12XHY Series

Page 1: ...MC9S12XHY Family MC9S12XHY256RMV1 Rev 1 01 03 2011 Data Sheet Advance Information This document contains information on a new product Specifications and information here in are subject to change witho...

Page 2: ...item update Table A 11 Pseudo Stop and Full Stop Current 10a 10b 11 12 13 14 remove temperature except 40 25 150 15 change to FSP mode remove Typeical Run supply table update Table A 11 Pseudo Stop an...

Page 3: ...ed in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be...

Page 4: ...MC9S12XHY Family Reference Manual Rev 1 01 4 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 5: ...and Reset Generator S12XECRGV2 259 Chapter 8 Pierce Oscillator S12XOSCLCPV2 289 Chapter 9 Voltage Regulator S12VREGL3V3V1 297 Chapter 10 Analog to Digital Converter ADC12B12CV1 315 Chapter 11 Freesca...

Page 6: ...12XFTMR128K1V1 619 Chapter 20 Motor Controller MC10B8CV1 667 Chapter 21 Stepper Stall Detector SSDV1 699 Appendix A Electrical Characteristics 717 Appendix B Package and Die Information 758 Appendix C...

Page 7: ...guration 61 1 17 Documentation Note 62 Chapter 2 Port Integration Module S12XHYPIMV1 2 1 Introduction 66 2 2 External Signal Description 67 2 3 Memory Map and Register Definition 74 2 4 Functional Des...

Page 8: ...al Description 261 7 3 Memory Map and Registers 262 7 4 Functional Description 276 7 5 Resets 284 7 6 Interrupts 287 Chapter 8 Pierce Oscillator S12XOSCLCPV2 8 1 Introduction 289 8 2 External Signal D...

Page 9: ...nctional Description 410 12 5 Resets 415 12 6 Interrupts 415 12 7 Application Information 416 Chapter 13 Pulse Width Modulator S12PWM8B8CV1 13 1 Introduction 423 13 2 External Signal Description 424 1...

Page 10: ...onal Description 557 17 5 Resets 567 17 6 Interrupts 567 Chapter 18 256 KByte Flash Module S12XFTMR256K1V1 18 1 Introduction 569 18 2 External Signal Description 572 18 3 Memory Map and Registers 572...

Page 11: ...y 720 A 1 7 Operating Conditions 721 A 1 8 Power Dissipation and Thermal Characteristics 722 A 1 9 I O Characteristics 724 A 1 10 Supply Currents 726 A 2 ATD Characteristics 731 A 2 1 ATD Operating Ch...

Page 12: ...Layout Guidelines C 1 General 765 C 1 1 112 Pin LQFP Recommended PCB Layout 766 C 1 2 100 Pin QFP Recommended PCB Layout 767 Appendix D Derivative Differences D 1 Memory Sizes and Package Options 9S1...

Page 13: ...performance The MC9S12XHY family features a 40x4 liquid crystal display LCD controller driver and a motor pulse width modulator MC consisting of up to 16 high current outputs The device is capable of...

Page 14: ...1 1 MC9S12XHY Family Feature MC9S12XHY128 MC9S12XHY256 CPU HCS12X V1 Flash memory ECC 128Kbytes 256 Kbytes Data flash ECC 8 Kbytes RAM 8 Kbytes 12kbyte Pin Quantity 100 112 100 112 CAN 2 SCI 2 SPI 1 I...

Page 15: ...PWM motor controller MC with up to 16 high current drivers Output slew rate control on Motor driver pad One serial peripheral interface SPI module One Inter IC bus interface IIC module Two serial com...

Page 16: ...error correction and double fault bit detection Erase sector size 1024bytes Automated program and erase algorithm Protection scheme to prevent accidental program or erase Security option to prevent u...

Page 17: ...f clock mode 1 3 7 System Integrity Support Power on reset POR System reset generation Illegal address detection with reset Low voltage detection with interrupt or reset Real time interrupt RTI Comput...

Page 18: ...ithering Output slew rate control 1 3 12 Pulse Width Modulation Module PWM 8channel x 8 bit or 4channel x 16 bit pulse width modulator Programmable period and duty cycle per channel Center aligned or...

Page 19: ...h Programmable polarity for transmitter and receiver Active edge receive wakeup Break detect and transmit collision detect supporting LIN 1 3 16 Serial Peripheral Interface Module SPI Configurable 8 o...

Page 20: ...ddress bus and 16 bit data bus with mask register Three modes simple address data match inside address range or outside address range 1 3 21 SSD Programmable Full Step State Programmable Integration p...

Page 21: ...Device Overview MC9S12XHY Family MC9S12XHY Family Reference Manual Rev 1 01 Freescale Semiconductor 21 Downloaded from Elcodis com electronic components distributor...

Page 22: ...odule 3 address breakpoints 1 data breakpoints 64 Byte Trace Buffer Reset Generation and Test Entry RXD TXD PR3 PR0 PR1 PR2 PTR KWU PR4 PR5 Synchronous Serial IF Auto Periodic Int PT3 PT0 PT1 PT2 PTT...

Page 23: ...TIM0 timer module 48 773 0x0070 0x009F ATD analog to digital converter 10 bit 8 channel 48 775 0x00A0 0x00C7 PWM pulse width modulator 8 channels 40 776 0x00C8 0x00CF SCI0 serial communications inter...

Page 24: ...nal resources in the memory map Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return undefined data values A CPU access to any unimplemented space causes an illegal address reset T...

Page 25: ...vice FLASH_LOW SIZE PPAGE 1 1 Number of 16K pages addressable via PPAGE register RAM_LOW SIZE RPAGE 2 2 Number of 4K pages addressing the RAM DF_HIGH SIZE EPAGE 3 3 Number of 1K pages addressing the D...

Page 26: ...F_FFFF CPU and BDM Local Memory Map FLASH FLASHSIZE Unimplemented FLASH 0xFFFF Vectors 0xC000 0x8000 Unpaged 0x4000 0x1000 0x0000 16K FLASH window 0x2000 0x0800 8K RAM 4K RAM window 2K REGISTERS 16K F...

Page 27: ...number indicates a specific version of internal NVM controller 1 7 Signal Description This section describes signals that connect off chip It includes a pinout diagram a table of signal properties an...

Page 28: ...0P PU5 M1SINM M1C1M IOC0_3 PU6 M1SINP M1C1P PU7 M2COSM M2C0M IOC0_4 IOC1_0 SCL PWM4 MISO PV0 M2COSP M2C0P MOSI PWM5 PV1 M2SINM M2C1M IOC0_5 IOC1_1 SCK PWM6 PV2 M2SINP M2C1P SDA PWM7 SS PV3 VDDM2 VSSM2...

Page 29: ...FP9 KWT1 IOC1_5 PT1 FP10 KWT2 IOC1_6 PT2 FP11 KWT3 IOC1_7 PT3 FP12 KWR4 PR4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85...

Page 30: ...12 8 8 Port A 8 8 Port B 8 6 Port H 8 8 Port P 8 8 Port R 8 6 Port S 8 8 Port T 8 8 Port U 8 8 Port V 8 8 Port M 4 0 Sum of Ports 88 76 I O Power Pairs VDDM VSSM 2 2 2 2 I O Power Pairs VDDX VSSX 2 2...

Page 31: ...M0 5 4 TIM0 3 2 TIM1 7 6 TIM1 3 2 SPI PWM 7 4 PWM 3 0 SCI1 PR 6 5 O PV 3 0 O PS 7 4 X2 23 PT 7 6 X2 16 PR 1 0 O PV6 PV4 O PT 5 4 X2 16 PV2 PV0 O PU6 PU4 X2 72 PM 1 0 O PT 3 2 X2 16 PR 3 2 O PV6 PV4 X2...

Page 32: ...wakeup 4 PAD08 AN08 VDDA PERAD Dis abled Port AD I O analog input of ATD 5 PAD09 AN09 VDDA PERAD Dis abled Port AD I O analog input of ATD 6 PAD10 AN10 VDDA PERAD Dis abled Port AD I O analog input of...

Page 33: ...abled Port V I O Motor2 coil nodes of MC MISO of SPI SCL of IIC PWM channel 4 TIM0 1 channel 20 16 PV1 PWM5 MOS I M2C 0P M2C OSP VDDM PERV P PSV Dis abled Port V I O Motor2 coil nodes of MC MOSI of S...

Page 34: ...PSP Down Port R I O timer1 Channel Key wakeup 31 27 PP2 PWM2 FP2 VDDX PERP P PSP Down Port P I O LCD Frontplane driver PWM channel 32 28 PP3 PWM3 FP3 VDDX PERP P PSP Down Port P I O LCD Frontplane dr...

Page 35: ...S3 PWM5 TXC AN0 KWS 3 VDDX PERS P PSS Up Port S I O PWM channel 5 TX of CAN0 Key wakeup 45 39 PR0 IOC0_ 6 RXC AN1 KWR 0 VDDX PERR P PSR Down Port R I O timer0 Chan nel RX of CAN1 Key wakeup 46 40 PR1...

Page 36: ...FP10 VDDX PERT P PST Down Port T I O LCD Frontplane driver timer1 channel key wakeup 55 49 PT3 IOC1_ 7 KWT 3 FP11 VDDX PERT P PST Down Port T I O LCD Frontplane driver timer1 channel key wakeup 56 50...

Page 37: ...n Port H I O LCD Frontplane driver MISO of SPI RXD of SCI1 64 58 PH1 MOSI TXD 1 FP20 VDDX PERH P PSH Down Port HI O LCD Frontplane driver MOSI of SPI TXD of SCI1 65 59 PH2 ECLK SCK FP21 VDDX PERH P PS...

Page 38: ...anne 3 73 63 VSSX1 74 64 VDDX1 75 65 PH4 FP23 VDDX PERH P PSH Down Port HI O LCD Frontplane driver 76 66 PH5 FP24 VDDX PERH P PSH Down Port H I O LCD Frontplane driver 77 67 VDDR 78 68 VSS3 79 69 VSS...

Page 39: ...t A I O LCD Frontplane driver 89 79 PA2 FP31 VDDX PUCR Down Port A I O LCD Frontplane driver 90 80 PA3 API_E XTCL K XCL KS FP32 VDDX PUCR Down Port A I O LCD Frontplane driver 91 81 PA4 FP33 VDDX PUCR...

Page 40: ...90 PB6 BP2 VDDX PUCR Down Port B I O LCD Backplane driver 103 91 PB7 BP3 VDDX PUCR Down Port B I O LCD Backplane driver 104 92 VLCD VDDX Voltage reference pin for the LCD driver 105 93 BKGD MODC VDDX...

Page 41: ...O analog input of ATD key wakeup 112 10 0 PAD04 AN04 KWA D4 VDDA PERAD Dis abled Port AD I O analog input of ATD key wakeup 1 Table shows a superset of pin functions Not all functions are available o...

Page 42: ...MCU operating mode select pin during reset The state of this pin is latched to the MODC bit at the rising edge of RESET The BKGD pin has an internal pull up device 1 7 3 5 PAD 7 0 AN 7 0 KWAD 7 0 Port...

Page 43: ...s They can be configured as frontplane segment driver output FP 39 37 28 1 7 3 12 PS7 PWM3 SDA SS Port S I O Pin 7 PS7 is a general purpose input or output pin It can be configured as the slave select...

Page 44: ...in It can be configured as the receive pin RXD of serial communication interface SCI It can be configured as PWM channel 6 1 7 3 20 PR7 FP 27 Port R I O Pin 7 PR7 is a general purpose input or output...

Page 45: ...t or output pin It can be configured as frontplane segment driver output FP 22 It can be configured as the slave selection pin SS for the serial peripheral interface SPI 1 7 3 30 PH2 ECLK SCK FP 21 Po...

Page 46: ..._2 RXD1 Port M I O Pins 0 PM0 is a general purpose input or output pin It can be configured as the receive pin RXD of serial communication interface SCI It can be configured as timer TIM0 channels 2 I...

Page 47: ...or to measure the back EMF to calibrate the pointer reset position The pin interfaces to the coils of motor 0 It can aslo be configured as timer TIM0 channel 1 1 7 3 45 PU 1 M0C0P M0COSP Port U I O Pi...

Page 48: ...gured as PWM channel 7 1 7 3 52 PV2 PWM6 SCK IOC1_1 IOC0_5 M2C1M M2SINM Port V I O Pin 2 PV2 is a general purpose input or output pin It can be configured as high current PWM output pin which can be u...

Page 49: ...l voltage regulator 1 7 4 3 VDD VSS2 VSS3 Core power Pins The voltage supply of nominally 1 8V is derived from the internal voltage regulator The return current path is through the VSS2 and VSS3 pin N...

Page 50: ...ary Mnemonic Nominal Voltage Description VDDR 5 0 V External power supply to internal voltage regulator VDDX 2 1 5 0 V External power and ground supply to pin drivers VSSX 2 1 0 V VDDA VRH 5 0 V Opera...

Page 51: ...1 5 shows the clock connections from the CRG to all modules Consult the S12XECRG section for details on clock generation NOTE The XHY and XS family uses the XE family clock and reset generator module...

Page 52: ...of no oscillator clock being present In addition to the clock monitor the MCU also provides a clock quality checker which performs a more accurate check of the clock The clock quality checker counts a...

Page 53: ...res the reset vector to be programmed correctly The processor program is executed from internal memory 1 9 1 2 Special Single Chip Mode This mode is used for debugging single chip operation boot strap...

Page 54: ...Full Stop Mode The oscillator is stopped in this mode By default all clocks are switched off and all counters and dividers remain frozen The Autonomous Periodic Interrupt API and ATD module may be ena...

Page 55: ...ction 5 4 1 Security and Section 15 5 Security 1 11 Resets and Interrupts Consult the S12X CPU manual and the S12XINT section for information on exception processing NOTE When referring to the S12XINT...

Page 56: ...base E8 TIM0 timer channel 3 I bit TIM0TIE C3I Vector base E6 TIM0 timer channel 4 I bit TIM0TIE C4I Vector base E4 TIM0 timer channel 5 I bit TIM0TIE C5I Vector base E2 TIM0 timer channel 6 I bit TI...

Page 57: ...timer channel 6 I bit TIM1TIE C6I Vector base A0 TIM1 timer channel 7 I bit TIM1TIE C7I Vector base 9E TIM1 timer overflow I bit TIM1TSRC2 TOF Vector base 9C TIM1 Pulse accumulator A overflow I bit TI...

Page 58: ...rature Interrupt HTI I bit VREGHTCL HTIE Vector base 7A CAN1 wake up I bit CANRIER WUPIE Vector base 78 CAN1 errors I bit CANRIER CSCIE OVRIE Vector base 76 CAN1 receive I bit CANRIER RXFIE Vector bas...

Page 59: ...the WCOP bit in the COPCTL registerare loaded from the Flash register FOPT See Table 1 12 and Table 1 13 for coding The FOPT register is loaded from the Flash configuration field byte at global addres...

Page 60: ...t global address 0x40_00F0 bits 5 0 during the reset sequence Currently factory programming of this IFR range is not supported Read access to reserved VREG register space returns 0 Write accesses have...

Page 61: ...on during reset low phase while a clock quality check is ongoing This is the case for Power on reset or low voltage reset Clock monitor reset Any reset while in self clock mode or full stop mode The s...

Page 62: ...e which those modules were designed to work with Please do not confuse them with the S12XHY product families S12XHY will support only 10 bit ATD resolution although in ATD12B block it still has the 12...

Page 63: ...te Section Table 1 5 Port Availability by Package Option VDD VSS2 fix Section 1 7 4 4 VDDF VSS1 NVM Power Pins fix Section 1 7 4 5 VDDA VSSA Power Supply Pins for ATD and Voltage Regulator update Sect...

Page 64: ...Device Overview MC9S12XHY Family MC9S12XHY Family Reference Manual Rev 1 01 64 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 65: ...re route on PM to PU PV SCI re route on PM to PH 0 07 29 Jul 2009 update by team review add SSD pin functions in pinmap update wire or options on port M 0 08 30 Jul 2009 fix add IOC1_1 IOC1_0 to Tabl...

Page 66: ...t H associated with 1 SPI 1 SCI Also associated with LCD driver output Port M associated with SCI1 PWM and TIM Port AD associated with one 12 channel ATD module It an be used as an external interrupt...

Page 67: ...and AD Control register to configure IRQ XIRQ pin operation Routing register to support module port relocation Free running clock outputs A standard port pin has the following minimum features Input o...

Page 68: ...egment driver output GPIO I O General purpose PA 1 FP 30 O LCD frontplane segment driver output XIRQ I Non maskable level sensitive interrupt GPIO I O General purpose PA 0 FP 29 O LCD frontplane segme...

Page 69: ...purpose PH 0 FP 19 O LCD frontplane segment driver output RXD1 I O Serial Communication Interface SCI1 receive pin MISO I O MISO of SPI mappable through software GPIO I O General purpose M PM 3 2 IOC1...

Page 70: ...GPIO I O General purpose PR 4 FP 12 I LCD frontplane segment driver output KWR4 I Key Wakeup GPIO I O General purpose PR 3 2 KWR 3 2 I Key Wakeup IOC1 7 6 I O TIM1 channel mappable through software G...

Page 71: ...l 5 mappable through software GPIO I O General purpose PS2 RXCAN0 I RX of CAN0 KWS2 I Key Wakeup PWM4 O PWM channel 4 mappable through software GPIO I O General purpose PS1 TXD0 I O Serial Communicati...

Page 72: ...O Motor control output for motor 1 IOC0_2 I O TIM0 channel2 GPIO I O General purpose PU 3 M0SINP I O SSD0 Sine Node M0C1P O Motor control output for motor 0 GPIO I O General purpose PU 2 M0SINM I O S...

Page 73: ...annel 7 mappable through software SS I O SS of SPI mappable through software GPIO I O General purpose PV2 M2SINM I O SSD2 sine node M2C1M O Motor control output for Motor 2 IOC0_5 I O TIM0 channel 5 I...

Page 74: ...ata Register R W 0x00 2 3 3 2 86 0x0001 PORTB Port B Data Register R W 0x00 2 3 4 2 87 0x0002 DDRA Port A Data Direction Register R W 0x00 2 3 5 2 87 0x0003 DDRB Port B Data Direction Register R W 0x0...

Page 75: ...104 0x024F PTSRR Port S Routing Register R W 0x00 2 3 29 2 104 M 0x0250 PTM Port M Data Register R W 0x00 2 3 31 2 106 0x0251 PTIM Port M Input Register R 3 2 3 32 2 107 0x0252 DDRM Port M Data Direc...

Page 76: ...Register R 0x00 2 3 58 2 124 0x0273 DDR1AD Port AD Data Direction Register R W 0x00 2 3 58 2 124 0x0274 PIM Reserved R 0x00 2 3 60 2 125 0x0275 PIM Reserved R W 0x00 2 3 42 2 113 0x0276 PER0AD Port AD...

Page 77: ...0x0295 PPSU Port U Polarity Select Register R W 0x00 2 3 86 2 140 0x0296 SRRU Port U Slew Rate Register R W 0x00 2 3 87 2 141 0x0297 PTURR Port S Routing Register PIM Reserved R 0x00 2 3 88 2 141 V 0...

Page 78: ...0 0 0 W 0x000A 0x000B Non PIM Address Range R Non PIM Address Range W 0x000C PUCR R 0 BKPUE 0 0 0 0 PUPBE PUPAE W 0x000D Reserved R 0 0 0 0 0 0 0 0 W 0x000E 0x001B Non PIM Address Range R Non PIM Addr...

Page 79: ...T5 PERT4 PERT3 PERT2 PERT1 PERT0 W 0x0245 PPST R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W 0x0246 Reserved R 0 0 0 0 0 0 0 0 W 0x0247 PTTRR R PTTRR7 PTTRR6 PTTRR5 PTTRR4 PTTRR3 PTTRR2 PTTRR1 P...

Page 80: ...R 0 0 0 0 DDRM3 DDRM2 DDRM1 DDRM0 W 0x0253 Reserved R 0 0 0 0 0 0 0 0 W 0x0254 PERM R 0 0 0 0 PERM3 PERM2 PERM1 PERM0 W 0x0255 PPSM R 0 0 0 0 PPSM3 PPSM2 PPSM1 PPSM0 W 0x0256 WOMM R 0 0 0 0 0 0 WOMM1...

Page 81: ...TIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 W 0x0262 DDRH R DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 W 0x0263 Reserved R PIM Reserved W 0x0264 PERH R PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 W 0x...

Page 82: ...D2 PER1AD1 PER1AD0 W 0x0278 0x027F Reserved R 0 0 0 0 0 0 0 0 W 0x0280 PTR R PTR7 PTR6 PTR5 PTR4 PTR3 PTR2 PTR1 PTR0 W 0x0281 PTIR R PTIR7 PTIR6 PTIR5 PTIR4 PTIR3 PTIR2 PTIR1 PTIR0 W 0x0282 DDRR R DDR...

Page 83: ...F1AD2 PIF1AD1 PIF1AD0 W 0x028E PIER R 0 0 0 0 PIER3 PIER2 PIER1 PIER0 W 0x028F PIFR R 0 0 0 0 PIFR3 PIFR2 PIFR1 PIFR0 W 0x0290 PTU R PTU7 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0 W 0x0291 PTIU R PTIU7 PTIU6...

Page 84: ...er a pull up or pull down device if PE is active 0x0297 PTURR R 0 0 0 0 PTURR3 PTURR2 0 0 W 0x0298 PTV R PTV7 PTV6 PTV5 PTV4 PTV3 PTV2 PTV1 PTV0 W 0x0299 PTIV R PTIV7 PTIV6 PTIV5 PTIV4 PTIV3 PTIV2 PTI...

Page 85: ...t A B and always 0 on AD IE3 3 Applicable only on Port T S R M and AD Function Pull Device Interrupt 0 x x 0 x 0 Input Disabled Disabled 0 x x 1 0 0 Input Pull Up Disabled 0 x x 1 1 0 Input Pull Down...

Page 86: ...bit otherwise the buffered pin input state is read The LCD segment driver output takes precedence over the API_EXTCLK and general purpose I O function if the related LCD segment is enabled The API_EXT...

Page 87: ...input output data Data Register LCD segment driver output The associated pin can be used as general purpose I O when not used as alternative function In general purpose output mode the register bit v...

Page 88: ...s output 0 Associated pin is configured as input 1 DDRA Port A Data Direction This bit determines whether the associated pin is an input or output If corresponding LCD segment is enabled it will be fo...

Page 89: ...ng LCD segment is enabled it will be forced as input output disabled 1 Associated pin is configured as output 0 Associated pin is configured as input Address 0x0004 PRR to 0x0009 PRR Access User read1...

Page 90: ...s bit configures whether a pull down device is activated on all associated port input pins If a pin is used as output this bit has no effect 1 pull down device enabled 0 pull down device disabled 0 PU...

Page 91: ...bus clock 1 ECLK disabled 0 ECLK enabled 5 DIV16 Free running ECLK predivider Divide by 16 This bit enables a divide by 16 stage on the selected EDIV rate 1 Divider enabled ECLK rate EDIV rate divided...

Page 92: ...able 2 10 IRQCR Register Field Descriptions Field Description 7 IRQE IRQ select edge sensitive only Special mode Read or write anytime Normal mode Read anytime write once 1 IRQ pin configured to respo...

Page 93: ...nimplemented or Reserved Figure 2 11 PIM Reserved Register Address 0x0240 Access User read write1 1 Read Anytime The data source is depending on the data direction value Write Anytime 7 6 5 4 3 2 1 0...

Page 94: ...output data Data Register LCD segment driver output TIM1 output When not used with the alternative function the associated pin can be used as general purpose I O In general purpose output mode the re...

Page 95: ...This bit determines whether the pin is an input or output If corresponding LCD segment is enabled it will be forced as input output disabled Else If corresponding TIM0 output compare channel is enabl...

Page 96: ...r a pull device on the associated port input pin is active If a pin is used as output this bit has no effect The polarity is selected by the related polarity select register bit 1 Pull device enabled...

Page 97: ...1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PTTRR7 PTTRR6 PTTRR5 PTTRR4 PTTRR3 PTTRR2 PTTRR1 PTTRR0 W Routing Option IOC0_7 IOC0_5 IOC0_4 IOC0_6 IOC1_7 IOC1_6 Reset 0 0 0 0 0 0 0 0 Unimplemented...

Page 98: ...ster controls the routing of IOC1_7 0 IOC1_7routed to PT3 1 IOC1_7 routed to PR3 0 PTTRR Port T data direction This register controls the routing of IOC1_6 0 IOC1_6 routed to PT2 1 IOC1_6 routed to PR...

Page 99: ...a read returns the value of the port register bit otherwise the buffered pin input state is read The SPI takes precedence over the PWM1 and the general purpose I O function if enabled The PWM1 takes...

Page 100: ...as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit oth...

Page 101: ...pin 6 This register configures pin as either input or output If SPI is routing to PS and SPI is enabled the SPI determines the pin direction Else if PWM2 is routing to PS and PWM2 is enabled it will...

Page 102: ...Port S data direction This register controls the data direction of pin 1 This register configures pin as either input or output If SCI is enabled it will force the pin as output Else if PWM7 is routin...

Page 103: ...bled 1 Pull device enabled 0 Pull device disabled Address 0x024D Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W Reset 0 0 0 0...

Page 104: ...WOMS Port S wired or mode Enable wired or functionality This register configures the output pins as wired or If enabled the output is driven active low only open drain A logic level of 1 is not driven...

Page 105: ...Reserved Register IIC x x 0 0 PS4 PS7 x x 0 1 PS4 PS7 x x 1 0 PR6 PR5 x x 1 1 PV0 PV3 MISO MOSI SCK SS SPI 0 0 x x PS4 PS5 PS6 PS7 0 1 x x PH0 PH1 PH2 PH3 1 0 x x PV0 PV1 PV2 PV3 1 1 x x Reserved Tabl...

Page 106: ...ion bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read The TIM1 output function takes precedence over the PWM7 and general purpose I O fun...

Page 107: ...ue is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read The SCI1 takes precedence over...

Page 108: ...3 2 DDRM Port M data direction This bit determines whether the pin is an input or output If corresponding LCD segment is enabled it will be forced as input output disabled Else If corresponding output...

Page 109: ...d Anytime Write Anytime 7 6 5 4 3 2 1 0 R 0 0 0 0 PERM3 PERM2 PERM1 PERM0 W Reset 0 0 0 0 1 1 1 1 Unimplemented or Reserved Figure 2 32 Port M Pull Device Enable Register PERM Table 2 28 PERT Register...

Page 110: ...ull down device if enabled on the associated port input pin 1 A pull down device is selected 0 A pull up device is selected Address 0x0256 Access User read1 1 Read Always reads 0x00 Write Unimplemente...

Page 111: ...ta Register PTP Table 2 31 PTP Register Field Descriptions Field Description 7 0 PTP Port P general purpose input output data Data Register LCD segment driver output PWM channel output Port P pins are...

Page 112: ...or Reserved u Unaffected by reset Figure 2 37 Port P Input Register PTIP Table 2 32 PTIP Register Field Descriptions Field Description 7 0 PTIP Port P input data This register always reads back the bu...

Page 113: ...be an input In these cases the data direction bit will not change 1 Associated pin is configured as output 0 Associated pin is configured as input 6 0 DDRP Port P data direction If enabled the LCD se...

Page 114: ...Reset 1 1 1 1 1 1 1 1 Figure 2 41 Port P Polarity Select Register PPSP Table 2 35 PPSP Register Field Descriptions Field Description 7 0 PPSP Port P pull device select Determine pull device polarity...

Page 115: ...3 PTPRRL2 PTPRRL1 PTPRRL0 W Reset 0 0 0 0 0 0 0 0 Figure 2 43 Port P Routing Register Low PTPRRL Table 2 37 PTPRRL Register Field Descriptions Field Description 3 0 PTPRRL Port P Routing Register Low...

Page 116: ...x 0 x x PP2 x x x x x x x x x 1 x x PS6 PWM1 x x x x x x x x x x 0 x PP1 x x x x x x x x x x 1 x PS5 PWM0 x x x x x x x x x x x 0 PP0 x x x x x x x x x x x 1 PS4 Address 0x0260 Access User read write1...

Page 117: ...the port register otherwise the buffered pin input state is read The LCD segment driver output takes precedence over the SPI ECLK and the general purpose I O function The SCK of SPI takes precedence...

Page 118: ...or Reserved u Unaffected by reset Figure 2 45 Port H Input Register PTIH Table 2 40 PTIH Register Field Descriptions Field Description 7 0 PTIH Port H input data This register always reads back the bu...

Page 119: ...nt output it will force the I O state to be a input output disabled Else if the SPI is routing to PH and SPI is enabled the SPI will determine the pin direction Else if ECLK is enabled it will force t...

Page 120: ...PERH2 PERH1 PERH0 W Reset 1 1 1 1 1 1 1 1 Figure 2 48 Port H Pull Device Enable Register PERH Table 2 42 PERH Register Field Descriptions Field Description 7 0 PERH Port H pull device enable Enable p...

Page 121: ...d Port H pin sets the associated flag bit in the PIFH register A pull up device is connected to the associated Port H pin if enabled by the associated bit in register PERH and if the port is used as i...

Page 122: ...0 PTHRR0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 2 51 Port HRouting Register PTHRR Table 2 45 Port H Routing Register Field Descriptions Field Description 0 PTHRR Port H Routing Regi...

Page 123: ...ta Register ATD AN analog input When not used with the alternative function the associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the...

Page 124: ...gister bit value is driven to the pin If the associated data direction bit is set to 1 a read returns the value of the port register bit otherwise the buffered pin input state is read Address 0x0272 A...

Page 125: ...AD0 W Reset 0 0 0 0 0 0 0 0 Figure 2 56 Port AD Data Direction Register DDR1AD Table 2 49 DDR1AD Register Field Descriptions Field Description 7 0 DDR1AD Port AD data direction This bit determines whe...

Page 126: ...W Reset 0 0 0 0 0 0 0 0 Figure 2 59 Port AD Pull Up Enable Register PER0AD Table 2 50 PER0AD Register Field Descriptions Field Description 3 0 PER0AD Port AD pull up enable Enable pull up device on i...

Page 127: ...lated polarity select register bit 1 Pull device enabled 0 Pull device disabled Address 0x0278 0x27F Access User read1 1 Read Always reads 0x00 Write Unimplemented 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W...

Page 128: ...A of IIC When not used with the alternative function the associated pin can be used as general purpose I O In general purpose output mode the register bit value is driven to the pin If the associated...

Page 129: ...the value of the port register bit otherwise the buffered pin input state is read The RX of CAN1 function takes precedence over the TIM0 and general purpose I O function The TIM0 output compare funct...

Page 130: ...d it will force as open drain output 1 Associated pin is configured as output 0 Associated pin is configured as input 5 DDRR Port R data direction This register controls the data direction of pin 5 Th...

Page 131: ...ociated pin is configured as input 0 DDRR Port R data direction This register controls the data direction of pin 3 0 This register configures pin as either input or output If TIM1 TIM0 are routing to...

Page 132: ...1 1 1 1 1 1 Figure 2 67 Port R Polarity Select Register PPSR Table 2 56 PPSR Register Field Descriptions Field Description 7 0 PPSR Port R pull device select Determine pull device polarity on input pi...

Page 133: ...tputs 0 Output buffers operate as push pull outputs Address 0x0287 Access User read1 1 Read Always reads 0x00 Write Unimplemented 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemente...

Page 134: ...this flag write logic level 1 to the corresponding bit in the PIFS register Writing a 0 has no effect 1 1 Active edge on the associated bit has occurred an interrupt will occur if the associated enabl...

Page 135: ...SS register To clear this flag write logic level 1 to the corresponding bit in the PIFS register Writing a 0 has no effect 1 Active edge on the associated bit has occurred an interrupt will occur if t...

Page 136: ...1 to the corresponding bit in the PIF1AD register Writing a 0 has no effect 1 1 Active falling edge on the associated bit has occurred an interrupt will occur if the associated enable bit is set 0 No...

Page 137: ...pin This could be a rising or a falling edge based on the state of the PPSR register To clear this flag write logic level 1 to the corresponding bit in the PIFR register Writing a 0 has no effect 1 A...

Page 138: ...used as general purpose I O If the associated data direction bits of these pins are set to 1 a read returns the value of the port register otherwise the buffered pin input state is read The SSD takes...

Page 139: ...escriptions Field Description 7 5 3 1 DDRU Port U data direction If enabled the Motor driver PWM output it will force the I O state to be output 1 Associated pin is configured as output 0 Associated p...

Page 140: ...vice is enabled 1 Pull device enabled 0 Pull device disabled Address 0x0295 Access User read write1 1 Read Anytime Write Anytime 7 6 5 4 3 2 1 0 R PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0 W Res...

Page 141: ...e digital input buffer 0 Disable the slew rate control and enable the digital input buffer 1 When change SRRU from non zero value to zero value or vice versa It will need to wait about 300 nanoseconds...

Page 142: ...ort M U Table 2 72 Port U Routing Register Field Descriptions Field Description 2 PTURR Port U Routing Register This register controls the routing of IOC0_2 0 IOC0_2 routed to PU4 1 IOC0_2 routed to P...

Page 143: ...eturns the value of the port register otherwise the buffered pin input state is read The SSD takes precedence over the Motor Driver and general purpose I O function The Motor driver PWM takes preceden...

Page 144: ...rt V general purpose input output data Data Register Motor driver PWM output TIM1 channel 1 SCK of SPI PWM channel 6 Port V pin 2 is associated with the Motor PWM output SPI and PWM channel 7 When not...

Page 145: ...eneral purpose I O If the associated data direction bit of this pins is set to 1 a read returns the value of the port register otherwise the buffered pin input state is read The SSD takes precedence o...

Page 146: ...enabled the Motor driver PWM output it will force the I O state to be output 1 Associated pin is configured as output 0 Associated pin is configured as input 6 DDRV Port V data direction If enabled t...

Page 147: ...outing to PV and SPI is enabled SPI will determined the I O state Else if PWM6 is routing to PV it will force the I O state to be output 1 Associated pin is configured as output 0 Associated pin is co...

Page 148: ...PERV7 PERV6 PERV5 PERV4 PERV3 PERV2 PERV1 PERV0 W Reset 0 0 0 0 0 0 0 0 Figure 2 90 Port V Pull Device Enable Register PERV Table 2 76 PERV Register Field Descriptions Field Description 7 0 PERV Port...

Page 149: ...e Anytime 7 6 5 4 3 2 1 0 R SRRV7 SRRV6 SRRV5 SRRV4 SRRV3 SRRV2 SRRV1 SRRV0 W Reset 0 0 0 0 0 0 0 0 Figure 2 92 Port V Polarity Select Register SRRV Table 2 78 SRRV Register Field Descriptions Field D...

Page 150: ...configuration might not become active For example selecting a pull up device This device does not become active while the port is used as a push pull output Address 0x029F Access User read1 1 Read Al...

Page 151: ...controls the pin the contents of the data direction register is ignored Figure 2 94 Independent of the pin usage with a peripheral module this register determines the source of data when reading the a...

Page 152: ...This register selects either a pull up or pull down device if enabled It becomes only active if the pin is used as an input A pull up device can be activated if the pin is used as a wired or output 2...

Page 153: ...se refer to the device pinout section to determine the pin availability in the different package options 2 4 3 1 BKGD pin The BKGD pin is associated with the BDM module During reset the BKGD pin is us...

Page 154: ...rupt vector Interrupts can be used with the pins configured as inputs or outputs An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bi...

Page 155: ...condition is true on any pin individually Sample count 4 and interrupt enabled PIE 1 and interrupt flag not set PIF 0 2 5 Initialization Information 2 5 1 Port Data and Data Direction Register writes...

Page 156: ...Port Integration Module S12XHYPIMV1 MC9S12XHY Family Reference Manual Rev 1 01 156 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 157: ...ntrols the multi master priority accesses the selection of internal resources Internal buses including internal memories and peripherals are controlled in this module The local address space for each...

Page 158: ...evel 0 Voltage that corresponds to Boolean false state 0x Represents hexadecimal number x Represents logic level don t care Byte 8 bit data word 16 bit data local address based on the 64KB Memory Spac...

Page 159: ...uction set The 64KB visible at any instant can be considered as the local map accessed by the 16 bit CPU or BDM address The MMC module performs translation of the different memory mapping schemes to t...

Page 160: ...nals Some pins may not be bonded out in all implementations Table 3 2 outlines the pin names and functions It also provides a brief description of their operation Table 3 2 External Input Signals Asso...

Page 161: ...3 2 1 Bit 0 0x000A Reserved R 0 0 0 0 0 0 0 0 W 0x000B MODE R MODC 0 0 0 0 0 0 0 W 0x0010 GPAGE R 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0 W 0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 W 0x0012 Reserv...

Page 162: ...erating mode during RESET high inactive The external mode pin MODC determines the operating mode during RESET low active The state of the pin is latched into the respective register bit after the RESE...

Page 163: ...Figure 3 7 GPAGE Address Mapping Example 3 1 This example demonstrates usage of the GPAGE register LDX 0x5000 Set GPAGE offset to the value of 0x5000 MOVB 0x14 GPAGE Initialize GPAGE register with th...

Page 164: ...Addressing Mode MOVB 0x80 DIRECT Set DIRECT register to 0x80 Write once only Global data accesses to the range 0xXX_80XX can be direct Logical data accesses to the range 0x80XX are direct LDY 00 Load...

Page 165: ...global memory map 0 Not visible in the global memory map 1 Visible in the global memory map 5 DFIFRON Data Flash Information Row IFR visible in the global memory map Write Anytime This bit is used to...

Page 166: ...ecial access of the CALL and RTC instructions will be complete before the end of the instruction execution The reset value of 0xFE ensures that there is linear Flash space available between addresses...

Page 167: ...E 0x00 The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and 0x3FFF out of reset The fixed 4K page from 0x2000 0x2FFF of RAM is equivalent to page 254...

Page 168: ...ev 1 01 168 Freescale Semiconductor The two fixed 4KB pages 0xFE 0xFF contain unimplemented area in the range not occupied by RAM if RAMSIZE is less than 8KB Refer to Section 3 4 2 3 Implemented Memor...

Page 169: ...ter is effectively used to construct paged Data FLASH addresses in the Local map format Figure 3 16 EPAGE Address Mapping Address 0x0017 7 6 5 4 3 2 1 0 R EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 W Reset 1 1 1...

Page 170: ...and BDM Memory Map Scheme The BDM firmware lookup tables and BDM register memory locations share addresses with other modules however they are not visible in the global memory map during user s code e...

Page 171: ...aged 0x4000 0x1000 0x0000 16KB FLASH window 0x0C00 0x2000 0x0800 8KB RAM 4KB RAM window Reserved 2KB REGISTERS 1KB Data Flash window 16KB FLASH Unpaged 16KB FLASH 2KB REGISTERS 2KB RAM 253 4KB paged R...

Page 172: ...rrupt service routine must be located in unpaged memory unless the user is certain that the PPAGE register will be set to the appropriate value when the service routine is called However an interrupt...

Page 173: ...PAGE The generated global address is the result of concatenation of the CPU local address 15 0 with the GPAGE register 22 16 see Figure 3 7 BDM Global Addresses Based on the Global Page The seven BDMG...

Page 174: ...the on chip resources Please note that the memory spaces have fixed top addresses Table 3 10 Global Implemented Memory Space Internal Resource Address RAM RAM_LOW 0x10_0000 minus RAMSIZE1 1 RAMSIZE i...

Page 175: ...but the data will be undefined No misaligned word access from the BDM module will occur these accesses are blocked in the BDM module Refer to BDM Block Guide Misaligned word access to the last locatio...

Page 176: ...nd BDM Local Memory Map Global Memory Map FLASHSIZE RAMSIZE 0xFFFF Reset Vectors 0xC000 0x8000 Unpaged 0x4000 0x1000 0x0000 16K FLASH window 0x0C00 0x2000 0x0800 8K RAM 4K RAM window Reserved 2K REGIS...

Page 177: ...ers CPU BDM with the rest of the system master buses In addition the MMC handles all CPU read data bus swapping operations All internal resources are connected to specific target buses see Figure 3 20...

Page 178: ...truction the CPU performs the following steps 1 Writes the current PPAGE value into an internal temporary register and writes the new instruction supplied PPAGE value into the PPAGE register 2 Calcula...

Page 179: ...structions is therefore recommended when possible and CALL RTC instructions should only be used when needed The JSR and RTS instructions can be used to access subroutines that are already present in t...

Page 180: ...Memory Mapping Control S12XMMCV4 MC9S12XHY Family Reference Manual Rev 1 01 180 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 181: ...rity scheme can be used to implement nested interrupt capability where interrupts from a lower level are automatically blocked if a higher level interrupt is being processed Interrupt requests configu...

Page 182: ...implemented op code trap TRAP vector at address vector base 0x00F8 Three system reset vectors at addresses 0xFFFA 0xFFFE Determines the highest priority XGATE and interrupt vector requests drives the...

Page 183: ...ction 4 5 3 Wake Up from Stop or Wait Mode for details Stop Mode In stop mode the XINT module is frozen It is however capable of either waking up the CPU if an interrupt occurs or waking up the XGATE...

Page 184: ...s Interrupt Requests Interrupt Requests CPU Vector Address New IPL IPL Up to 108 Channels RQST XGATE Request Route PRIOLVLn Priority Level bits from the channel configuration in the associated configu...

Page 185: ...W 0x0127 Interrupt Request Configuration Address Register INT_CFADDR R W 0x0128 Interrupt Request Configuration Data Register 0 INT_CFDATA0 R W 0x0129 Interrupt Request Configuration Data Register 1...

Page 186: ...NT_CFADDR R INT_CFADDR 7 4 0 0 0 0 W 0x0128 INT_CFDATA0 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x0129 INT_CFDATA1 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012A INT_CFDATA2 R RQST 0 0 0 0 PRIOLVL 2 0 W 0x012B INT_CFDATA3...

Page 187: ...o determine the reset vector address Therefore changing the IVBR has no effect on the location of the three reset vectors 0xFFFA 0xFFFE Note If the BDM is active i e the CPU is in the process of execu...

Page 188: ...riority level 3 1 0 0 Priority level 4 1 0 1 Priority level 5 1 1 0 Priority level 6 high 1 1 1 Priority level 7 Address 0x0127 7 6 5 4 3 2 1 0 R INT_CFADDR 7 4 0 0 0 0 W Reset 0 0 0 1 0 0 0 0 Unimple...

Page 189: ...description below Unimplemented or Reserved Figure 4 7 Interrupt Request Configuration Data Register 1 INT_CFDATA1 Address 0x012A 7 6 5 4 3 2 1 0 R RQST 0 0 0 0 PRIOLVL 2 0 W Reset 0 0 0 0 0 0 0 1 1 1...

Page 190: ...PRIOLVL 2 0 description below Unimplemented or Reserved Figure 4 11 Interrupt Request Configuration Data Register 5 INT_CFDATA5 Address 0x012E 7 6 5 4 3 2 1 0 R RQST 0 0 0 0 PRIOLVL 2 0 W Reset 0 0 0...

Page 191: ...lowest active level 1 to provide backwards compatibility with previous S12 interrupt controllers Please also refer to Table 4 9 for available interrupt request priority levels Note Write accesses to c...

Page 192: ...2 The setup in the configuration register associated with the interrupt request channel must meet the following conditions a The XGATE request enable bit must be 0 to have the CPU handle the interrupt...

Page 193: ...the same time the channel with the highest vector address wins the prioritization 4 4 4 Priority Decoders The XINT module contains priority decoders to determine the priority for all interrupt reques...

Page 194: ...SWI BGND request SYS request there is no real priority defined because they cannot occur simultaneously the S12XCPU executes one instruction at a time Table 4 10 Exception Vector Map and Priority Vec...

Page 195: ...level scheme makes it possible to implement priority based interrupt request nesting for the I bit maskable interrupt requests handled by the CPU I bit maskable interrupt requests can be interrupted...

Page 196: ...interrupt request can wake up the MCU from stop or wait mode at anytime even if the X bit in CCR is set If the X bit maskable interrupt request is used to wake up the MCU with the X bit in the CCR set...

Page 197: ...mmand no longer supported by BDM External instruction tagging feature now part of DBG module BDM register map and register content extended modified Global page access functionality Enabled but not ac...

Page 198: ...lable in all operating modes but must be enabled before firmware commands are executed Some systems may have a control bit that allows suspending thefunction during background debug mode 5 1 2 1 Regul...

Page 199: ...art and BDM will have a soft reset clearing the instruction register any command in progress and disable the ACK function The BDM is now ready to receive a new command 5 1 3 Block Diagram A block diag...

Page 200: ...FFF00 0x7FFF0B BDM registers 12 0x7FFF0C 0x7FFF0E BDM firmware ROM 3 0x7FFF0F Family ID part of BDM firmware ROM 1 0x7FFF10 0x7FFFFF BDM firmware ROM 240 Global Address Register Name Bit 7 6 5 4 3 2 1...

Page 201: ...ry This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed 1 0 0 0 0 03 3 UNSEC is read as 1 by a debugging environment in special sing...

Page 202: ...t by BDM hardware out of reset In special single chip mode with the device secured this bit will not be set by the firmware until after the non volatile memory erase verify tests are complete In emula...

Page 203: ...modes if modes available the CLKSW bit will be set out of RESET 1 UNSEC Unsecure If the device is secured this bit is only writable in special single chip mode from the BDM secure firmware It is in a...

Page 204: ...e user s program It is also used for temporary storage in the standard BDM firmware mode The BDM CCR LOW holding register can be written to modify the CCR value 5 3 2 3 BDM CCR HIGH Holding Register B...

Page 205: ...d BDM Firmware Commands The CPU resources referred to are the accumulator D X index register X Y index register Y stack pointer SP and program counter PC Hardware commands can be executed at any time...

Page 206: ...d BDM firmware commands BDM can be activated only after being enabled BDM is enabled by setting the ENBDM bit in the BDM status BDMSTS register The ENBDM bit is set by writing to the BDM status BDMSTS...

Page 207: ...resources are enabled just for the READ_BD and WRITE_BD access cycle This allows the BDM to access BDM locations unobtrusively even if the addresses conflict with the application memory map Table 5 6...

Page 208: ...BDM the standard BDM firmware lookup table and BDM registers become visible in the on chip memory map at 0x7FFF00 0x7FFFFF and the CPU begins executing the standard BDM firmware The standard BDM firm...

Page 209: ...a out Read X index register READ_Y 66 16 bit data out Read Y index register READ_SP 67 16 bit data out Read stack pointer WRITE_NEXT f hel vetica st superscri pt 42 16 bit data in Increment X index re...

Page 210: ...host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data This includes the potential of extra cycles when the access is external an...

Page 211: ...data is transmitted or received Data is transferred most significant bit MSB first at 16 target clock cycles per bit The interface times out if 512 clock cycles occur between falling edges from the ho...

Page 212: ...get clock cycles later the target senses the bit level on the BKGD pin Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a...

Page 213: ...to Host Serial Bit Timing Logic 1 High Impedance Earliest Start of Next Bit R C Rise 10 Cycles 10 Cycles Host Samples BKGD Pin Perceived Start of Bit Time BKGD Pin BDM Clock Target MCU Host Drive to B...

Page 214: ...s sub section will describe the hardware handshake protocol The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target This protocol...

Page 215: ...ed by the address of the memory location to be read The target BDM decodes the instruction A bus cycle is grabbed free or stolen by the BDM and it executes the READ_BYTE operation Having retrieved the...

Page 216: ...provide a time out This means for the GO_UNTIL command that it can not be distinguished if a stop or wait has been executed command discarded and ACK not issued or if the UNTIL condition BDM active is...

Page 217: ...aborted the target assumes the next negative edge after the abort pulse is the first bit of a new BDM command NOTE The details about the short abort pulse are being provided only as a reference for th...

Page 218: ...thout the need for waiting for the ACK pulse The commands are described as follows ACK_ENABLE enables the hardware handshake protocol The target will issue the ACK pulse when a CPU command is executed...

Page 219: ...issued when the CPU enters background active mode after one instruction of the application program is executed The ACK pulse related to this command could be aborted using the SYNC command 5 4 9 SYNC...

Page 220: ...irmware execution the program counter points to the first instruction in the interrupt service routine Be aware when tracing through the user code that the execution of the user code is done step by s...

Page 221: ...d However consider the behavior where the BDM is running in a frequency much greater than the CPU frequency In this case the command could time out before the data is ready to be retrieved In order to...

Page 222: ...Background Debug Module S12XBDMV2 MC9S12XHY Family Reference Manual Rev 1 01 222 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 223: ...6 1 1 Glossary Revision Number Revision Date Sections Affected Description of Changes V03 20 14 Sep 2007 6 3 2 7 6 233 Clarified reserved State Sequencer encodings V03 21 23 Oct 2007 6 4 2 2 6 246 6...

Page 224: ...monitor CPU12X buses Each comparator features selection of read or write access cycles Comparators B and D allow selection of byte or word access cycles Comparisons can be used as triggers for the sta...

Page 225: ...uring BDM hardware accesses and whilst the BDM module is active CPU12X monitoring is disabled Thus breakpoints comparators and CPU12X bus tracing are disabled When the CPU12X enters active BDM Mode th...

Page 226: ...follow Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0020 DBGC1 R ARM 0 reserved BDM DBGBRK reserved COMRV W TRIG 0x0021 DBGSR R TBF 0 0 0 0 SSF2 SSF1 SSF0 W 0x0022 DBGTCR R reserved TSOURCE TRANGE TRCMOD T...

Page 227: ...X R 0 0 0 0 SC3 SC2 SC1 SC0 W 0x0027 DBGMFR R 0 0 0 0 MC3 MC2 MC1 MC0 W 0x00281 DBGXCTL COMPA C R 0 NDB TAG BRK RW RWE reserved COMPE W 0x00282 DBGXCTL COMPB D R SZE SZ TAG BRK RW RWE reserved COMPE W...

Page 228: ...ot enabled On setting this bit the state sequencer enters State1 0 Debugger disarmed 1 Debugger armed 6 TRIG Immediate Trigger Request Bit This bit when written to 1 requests an immediate trigger inde...

Page 229: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 4 Debug Status Register DBGSR Table 6 6 DBGSR Field Descriptions Field Description 7 TBF Trace Buffer Full The TBF bit indicates that...

Page 230: ...CU system is secured this bit cannot be set and tracing is inhibited 0 No tracing selected 1 Tracing selected 5 4 TRANGE Trace Range Bits The TRANGE bits allow filtering of trace information from a se...

Page 231: ...MOD Description 00 Normal 01 Loop1 10 Detail 11 Pure PC Table 6 11 TALIGN Trace Alignment Encoding TALIGN Description 00 Trigger at end of stored data 01 Trigger before storing data 10 Trace buffer en...

Page 232: ...comparator B Address 0x0024 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W POR X X X X X X X X X...

Page 233: ...lls over to zero the TBF bit in DBGSR is set and incrementing of CNT will continue in end trigger or mid trigger mode The DBGCNT register is cleared when ARM in DBGC1 is written to a one The DBGCNT re...

Page 234: ...ed by setting the comparator enable bit in the associated DBGXCTL control register Table 6 18 State Control Register Access Encoding COMRV Visible State Control Register 00 DBGSCR1 01 DBGSCR2 10 DBGSC...

Page 235: ...ggers to State3 Match0 triggers Final State Other matches have no effect 1010 Match1 triggers to State2 Match3 triggers to State3 Other matches have no effect 1011 Match3 triggers to State3 Match1 tri...

Page 236: ...ch0 triggers Final State Other matches have no effect 1000 Match0 triggers to State1 Match2 triggers to State3 Other matches have no effect 1001 Match2 triggers to State3 Match0 triggers Final State O...

Page 237: ...rs A and C consist of 8 register bytes 3 address bus compare registers two data bus compare registers two data bus mask registers and a control register 0010 Any match triggers to Final State 0011 Mat...

Page 238: ...Read Anytime See Table 6 26 for visible register encoding Write If DBG not armed See Table 6 26 for visible register encoding WARNING DBGXCTL 1 is reserved Setting this bit maps the corresponding com...

Page 239: ...parator register contents 6 SZ Comparators B and D Size Comparator Value Bit The SZ bit selects either word or byte access size in comparison for the associated comparator This bit is ignored if the S...

Page 240: ...rs or tag generation Table 6 28 Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write 1 0 1 No match 1 1 0 N...

Page 241: ...on 7 0 Bit 15 8 Comparator Address Mid Compare Bits The Comparator address mid compare bits control whether the selected comparator will compare the address bus bits 15 8 to a logic one or logic zero...

Page 242: ...bus bits 15 8 to a logic one or logic zero The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1 This register is available only for comparators A...

Page 243: ...gh Mask Register DBGXDHM Table 6 34 DBGXDHM Field Descriptions Field Description 7 0 Bits 15 8 Comparator Data High Mask Bits The Comparator data high mask bits control whether the selected comparator...

Page 244: ...Each comparator compares the selected address bus with the address stored in DBGXAH DBGXAM and DBGXAL Furthermore comparators A and C also compare the data buses to the data stored in DBGXDH DBGXDL an...

Page 245: ...ct Address Comparator Match Comparators A and C With range comparisons disabled the match condition is an exact equivalence of address data bus with the value stored in the comparator address data reg...

Page 246: ...n difference This allows monitoring of a difference in the contents of an address location from an expected value When matching on an equivalence NDB 0 each individual data bus bit position can be mas...

Page 247: ...ges are accurate only to word boundaries 6 4 2 4 1 Inside Range CompAC_Addr address CompBD_Addr In the Inside Range comparator mode either comparator pair A and B or comparator pair C and D can be con...

Page 248: ...register for the current state determines the next state for each trigger 6 4 3 3 TRIG Immediate Trigger Independent of comparator matches it is possible to initiate a tracing session and or breakpoi...

Page 249: ...ediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers Thus it is possible to generate an immediate breakpoint on selected channels whilst a state sequencer tra...

Page 250: ...ce buffer pointer is not incremented 6 4 5 1 Trace Trigger Alignment Using the TALIGN bits see Section 6 3 2 3 it is possible to align the trigger with the end the middle or the beginning of a tracing...

Page 251: ...nation address of RTI RTS and RTC instructions Vector address of interrupts except for SWI and BDM vectors LBRA BRA BSR BGND as well as non indexed JMP JSR and CALL instructions are not classified as...

Page 252: ...ranches Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs It does not inhibit repeated entries of destination addres...

Page 253: ...red whilst the other DBGCNT bits are incremented on each trace buffer entry When a COF occurs a trace buffer entry is made and the corresponding CDV bit is set Single byte data accesses in Detail Mode...

Page 254: ...g stored address is a source or destination address This is only used in Normal and Loop1 mode tracing 0 Source address 1 Destination address 6 CVA Vector Indicator This bit indicates if the correspon...

Page 255: ...invalid information shaded in Table 6 40 are also read out Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of the RAM pointer will occur 6 4 5 5 Tr...

Page 256: ...ize SZ monitoring and data bus monitoring is not useful if tagged triggering is selected since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on the...

Page 257: ...ctive the CPU12X is executing out of BDM firmware and S12X breakpoints are disabled In addition while executing a BDM TRACE command tagging into BDM is disabled If BDM is not active the breakpoint wil...

Page 258: ...aneously The CPU12X ensures that BDM requests have a higher priority than SWI requests Returning from the BDM SWI service routine care must be taken to avoid re triggering a breakpoint NOTE When progr...

Page 259: ...om locked condition Self Clock Mode in absence of reference clock System Clock Generator Clock Quality Check User selectable fast wake up from Stop in Self Clock Mode for power saving and immediate pr...

Page 260: ...clocks are stopped The COP and the RTI remain frozen Pseudo Stop Mode The oscillator continues to run and most of the system and core clocks are stopped If the respective enable bits are set the COP...

Page 261: ...properly 7 2 2 RESET RESET is an active low bidirectional reset pin As an input it initializes the MCU asynchronously to a known start up state As an open drain output it indicates that an system res...

Page 262: ...0001 REFDV R REFFRQ 1 0 REFDIV 5 0 W 0x0002 POSTDIV R 0 0 0 POSTDIV 4 0 W 0x0003 CRGFLG R RTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM W 0x0004 CRGINT R RTIE 0 0 LOCKIE 0 0 SCMIE 0 W 0x0005 CLKSEL R PLLS...

Page 263: ...aximum If POSTDIV 00 then fPLL is same as fVCO divide by one The VCOFRQ 1 0 bit are used to configure the VCO gain for optimal stability and lock time For correct IPLL operation the VCOFRQ 1 0 bits ha...

Page 264: ...uency as shown in Figure 7 3 Setting the REFFRQ 1 0 bits wrong can result in a non functional IPLL no locking and or insufficient stability 7 3 2 3 S12XECRG Post Divider Register POSTDIV The POSTDIV r...

Page 265: ...Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 7 5 S12XECRG Post Divider Register POSTDIV Module Base 0x0003 7 6 5 4 3 2 1 0 R RTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM W Reset 0 Note 1 Note...

Page 266: ...0 No change in LOCK bit 1 LOCK bit has changed 3 LOCK Lock Status Bit LOCK reflects the current state of IPLL lock condition This bit is cleared in Self Clock Mode Writes have no effect 0 VCOCLK is no...

Page 267: ...Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled 1 Interrupt will be requested whenever RTIF is set 4 LOCKIE Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled...

Page 268: ...cal stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption 5 XCLKS Oscillator Configuration Status Bit This read only bit shows...

Page 269: ...Fast wake up from full stop mode is disabled 1 Fast wake up from full stop mode is enabled When waking up from full stop mode the system will immediately resume operation in Self Clock Mode see Secti...

Page 270: ...Decimal or Binary Divider Select Bit RTDEC selects decimal or binary based prescaler values 0 Binary based divider value See Table 7 10 1 Decimal based divider value See Table 7 11 6 4 RTR 6 4 Real Ti...

Page 271: ...x212 14x213 14x214 14x215 14x216 1110 15 OFF 15x210 15x211 15x212 15x213 15x214 15x215 15x216 1111 16 OFF 16x210 16x211 16x212 16x213 16x214 16x215 16x216 1 Denotes the default value out of reset This...

Page 272: ...0 10 x103 20x103 50x103 100x103 200x103 500x103 1x106 2x106 1010 11 11 x103 22x103 55x103 110x103 220x103 550x103 1 1x106 2 2x106 1011 12 12x103 24x103 60x103 120x103 240x103 600x103 1 2x106 2 4x106 1...

Page 273: ...is in Active BDM mode 5 WRTMASK Write Mask for WCOP and CR 2 0 Bit This write only bit serves as a mask for the WCOP and CR 2 0 bits while writing the COPCTL register It is intended for BDM writing th...

Page 274: ...poses only and is not intended for general user access Writing to this register when in special test modes can alter the S12XECRG s functionality Read Always read 00 except in special modes 1 1 1 2 24...

Page 275: ...art the COP time out period you must write 55 followed by a write of AA Other instructions may be executed between these writes but the sequence 55 AA must be completed prior to COP end of time out pe...

Page 276: ...to generate the PLLCLK NOTE Although it is possible to set the dividers to command a very high clock frequency do not exceed the specified bus frequency limit for the MCU If PLLSEL 1 then fBUS fPLL 2...

Page 277: ...on this comparison If IPLL LOCK interrupt requests are enabled the software can wait for an interrupt request and then check the LOCK bit If interrupt requests are disabled software can poll the LOCK...

Page 278: ...in The Core Clock signal is the clock for the CPU The Core Clock is twice the Bus Clock But note that a CPU cycle corresponds to one Bus Clock IPLL clock mode is selected with PLLSEL bit in the CLKSEL...

Page 279: ...ck monitor performs a coarse check on the incoming clock signal The clock quality checker provides a more accurate check in addition to the clock monitor A clock quality check is triggered by any of t...

Page 280: ...Quality Checker enables the IPLL and the voltage regulator VREG anytime a clock check has to be performed An ongoing clock quality check could also cause a running IPLL fSCM and an active VREG during...

Page 281: ...reset the part If PCE bit is set the COP will continue to run in Pseudo Stop Mode 7 4 1 6 Real Time Interrupt RTI The RTI can be used to generate a hardware interrupt at a fixed periodic rate If enabl...

Page 282: ...e stopped by setting the associated rate select bits to zero 7 4 3 2 Wait Mode The WAI instruction puts the MCU in a low power consumption stand by mode depending on setting of the individual bits in...

Page 283: ...Clock Mode the ongoing clock quality check will be stopped A complete timeout window check will be started when Stop Mode is left again There are two ways to restart the MCU from Stop Mode 1 Any rese...

Page 284: ...Address Reset None Clock Monitor Reset PLLCTL CME 1 SCME 0 Oscillator Clock PLL Clock Core Clock Instruction STOP IRQ service FSTWKP 1 IRQ service STOP STOP IRQ service Oscillator Disabled Power Savi...

Page 285: ...s depending on the internal synchronization latency After 128 n SYSCLK cycles the RESET pin is released The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and then samples the R...

Page 286: ...ts As soon as clock quality check indicates a valid Oscillator Clock the S12XECRG switches to OSCCLK and leaves Self Clock Mode Since the clock quality checker is running in parallel to the reset gene...

Page 287: ...VDD and when the RESET pin is held low Figure 7 22 RESET Pin Tied to VDD by a Pull up Resistor Figure 7 23 RESET Pin Held Low Externally 7 6 Interrupts The interrupts reset vectors requested by the S1...

Page 288: ...e versa Lock interrupts are locally disabled by setting the LOCKIE bit to zero The IPLL Lock interrupt flag LOCKIF is set to1 when the LOCK condition has changed and is cleared to 0 by writing a 1 to...

Page 289: ...e gm sized for optimum start up margin for typical oscillators Dynamic gain control eliminates the need for external current limiting resistor Integrated resistor eliminates the need for external bias...

Page 290: ...for the XOSC circuitry This allows the supply voltage to the XOSC to use an independent bypass capacitor 8 2 2 EXTAL and XTAL Input and Output Pins These pins provide the interface for either a cryst...

Page 291: ...ntrolled Pierce Oscillator Connections LCP mode selected NOTE Full swing Pierce circuit is not suited for overtone resonators and crystals without a careful component selection Figure 8 3 Full Swing P...

Page 292: ...d whereby the amplifier is modulated to keep the output waveform sinusoidal and to limit the oscillation amplitude The output peak to peak voltage will be kept above twice the maximum hysteresis level...

Page 293: ...Pierce Oscillator S12XOSCLCPV2 MC9S12XHY Family Reference Manual Rev 1 01 Freescale Semiconductor 293 Downloaded from Elcodis com electronic components distributor...

Page 294: ...Pierce Oscillator S12XOSCLCPV2 MC9S12XHY Family Reference Manual Rev 1 01 294 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 295: ...Pierce Oscillator S12XOSCLCPV2 MC9S12XHY Family Reference Manual Rev 1 01 Freescale Semiconductor 295 Downloaded from Elcodis com electronic components distributor...

Page 296: ...Pierce Oscillator S12XOSCLCPV2 MC9S12XHY Family Reference Manual Rev 1 01 296 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 297: ...e modes VREG_3V3 can operate in 1 Full performance mode FPM MCU is not in stop mode The regulator is active providing the nominal supply voltages with full current sourcing capability Features LVD low...

Page 298: ...POR feature is available LVD LVR and HTD are disabled The API internal RC oscillator clock is not available This mode must be used to disable the chip internal regulator VREG_3V3 i e to bypass the VRE...

Page 299: ...LVI POR LVR CTRL VSS VDDPLL VSSPLL VREGEN REG PIN VDDA REG Regulator Core CTRL Regulator Control LVD Low Voltage Detect LVR Low Voltage Reset POR Power on Reset HTD High Temperature Detect C HTI HTD A...

Page 300: ...VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator Internal precision reference circuits are supplied from these signals A chip external decoupling ca...

Page 301: ...h the LVR feature 9 2 7 VREGEN Optional Regulator Enable Pin This optional signal is used to shutdown VREG_3V3 In that case VDD VSS and VDDPLL VSSPLL must be provided externally Shutdown mode is enter...

Page 302: ...REGHTCL R 0 0 VSEL VAE HTEN HTDS HTIE HTIF W 0x02F1 VREGCTRL R 0 0 0 0 0 LVDS LVIE LVIF W 0x02F2 VREGAPIC L R APICLK 0 0 APIFES APIEA APIFE APIE APIF W 0x02F3 VREGAPIT R R APITR5 APITR4 APITR3 APITR2...

Page 303: ...Bit If set the voltage selected by bit VSEL can be accessed internally i e multiplexed to an internal Analog to Digital Converter channel See device level specification for connectivity 0 Voltage sel...

Page 304: ...it reflects the input voltage Writes have no effect 0 Input voltage VDDA is above level VLVID or RPM or shutdown mode 1 Input voltage VDDA is below level VLVIA and FPM 1 LVIE Low Voltage Interrupt Ena...

Page 305: ...iod Table 9 10 See device level specification for connectivity 0 At the external periodic high pulses are visible if APIEA and APIFE is set 1 At the external pin a clock is visible if APIEA and APIFE...

Page 306: ...nimplemented or Reserved Figure 9 4 Autonomous Periodical Interrupt Trimming Register VREGAPITR Table 9 7 VREGAPITR Field Descriptions Field Description 7 2 APITR 5 0 Autonomous Periodical Interrupt P...

Page 307: ...or Reserved Figure 9 5 Autonomous Periodical Interrupt Rate High Register VREGAPIRH 0x02F5 7 6 5 4 3 2 1 0 R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W Reset 0 0 0 0 0 0 0 0 Figure 9 6 Autonomo...

Page 308: ...ms1 1 When trimmed within specified accuracy See electrical specifications for details 0 0001 0 4 ms1 0 0002 0 6 ms1 0 0003 0 8 ms1 0 0004 1 0 ms1 0 0005 1 2 ms1 0 0 FFFD 13106 8 ms1 0 FFFE 13107 0 m...

Page 309: ...0 01 01 01 01 1 Reset value is either 0 or preset by factory See Section 1 Device Overview for details Unimplemented or Reserved Figure 9 8 VREGHTTR Table 9 11 VREGHTTR field descriptions Field Descri...

Page 310: ...ifier The amplified input voltage difference drives the gate of an output transistor 9 4 2 2 Reduced Power Mode In Reduced Power Mode the gate of the output transistor is connected directly to a refer...

Page 311: ...o enable the timer the bit APIFE needs to be set The API timer is either clocked by a trimmable internal RC oscillator or the bus clock Timer operation will freeze when MCU clock source is selected an...

Page 312: ...chip power up the digital core may not work if its supply voltage VDD is below the POR deassertion level VPORD Therefore signal POR which forces the other blocks of the device into reset is kept high...

Page 313: ...eared by the VREG_3V3 9 4 11 2 HTI High Temperature Interrupt In FPM VREG monitors the die temperature TDIE Whenever TDIE exceeds level THTIA the status bit HTDS is set to 1 Vice versa HTDS is reset t...

Page 314: ...Voltage Regulator S12VREGL3V3V1 MC9S12XHY Family Reference Manual Rev 1 01 314 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 315: ...time Left right justified result data External trigger control Sequence complete interrupt Analog input multiplexer for 8 analog input channels Special conversions for VRH VRL VRL VRH 2 Version Numbe...

Page 316: ...annel scans Configurable external trigger functionality on any AD channel or any of four additional trigger inputs The four additional trigger inputs can be chip external or internal Refer to device s...

Page 317: ...d etc ICLKSTP 1 in ATDCTL2 register A D conversion sequence seamless continues in Stop Mode based on the internally generated clock ICLK as ATD clock For conversions during transition from Run to Stop...

Page 318: ...esults ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 and DAC Sample Hold VDDA VRL VRH Sequence Complete Comparator Clock Prescaler Bus Clock ATD Clock AN5 AN4 AN3 AN1 AN0 AN7 ETRIG0 See device speci...

Page 319: ...nce voltage for ATD conversion 10 2 1 4 VDDA VSSA These pins are the power supplies for the analog circuitry of the ADC12B12C block 10 3 Memory Map and Register Definition This section provides a deta...

Page 320: ...M 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x0016 ATDDR3 R See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x0...

Page 321: ...ion 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x0026 ATDDR11 R See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x0028 0x002F...

Page 322: ...0 0 0 0 1 1 1 1 Unimplemented or Reserved Figure 10 3 ATD Control Register 0 ATDCTL0 Table 10 1 ATDCTL0 Field Descriptions Field Description 3 0 WRAP 3 0 Wrap Around Channel Select Bits These bits det...

Page 323: ...ot available writing a 1 to ETRISEL only sets the bit but has not effect this means that one of the AD channels selected by ETRIGCH3 0 is configured as the source for external trigger The coding is su...

Page 324: ...AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN8 0 1 0 0 1 AN9 0 1 0 1 0 AN10 0 1 0 1 1 AN11 0 1 1 0 0 AN11 0 1 1 0 1 AN11 0 1 1 1 0 AN11 0 1 1 1 1 AN11 1 0 0 0 0 ETRIG01 1 Only if ETRIG3 0 input option is available s...

Page 325: ...ing this time 0 If A D conversion sequence is ongoing when going into stop mode the actual conversion sequence will be aborted and automatically restarted when exiting stop mode 1 A D continues to con...

Page 326: ...onversion results are placed in consecutive result registers In a continuously scanning conversion sequence the result register counter will wrap around when it reaches the end of the result register...

Page 327: ...ution 1 25mV 5 120 Volts 0 022 0 020 0 018 0 016 0 014 0 012 0 010 0 008 0 006 0 004 0 003 0 002 0 000 255 1 1 1 1 1 1 1 0 0 0 0 0 0 1023 4 4 4 3 3 2 2 2 1 1 0 0 0 4095 17 16 14 12 11 9 8 6 4 3 2 1 0...

Page 328: ...Table 10 12 ATDCTL4 Field Descriptions Field Description 7 5 SMP 2 0 Sample Time Select These three bits select the length of the sample time in units of ATD conversion clock cycles Note that the ATD...

Page 329: ...erved Figure 10 8 ATD Control Register 5 ATDCTL5 Table 10 14 ATDCTL5 Field Descriptions Field Description 6 SC Special Channel Conversion Bit If this bit is set then special channel conversion can be...

Page 330: ...ut channel s whose signals are sampled and converted to digital codes Table 10 15 lists the coding used to select the various analog input channels In the case of single channel conversions MULT 0 thi...

Page 331: ...reescale Semiconductor 331 1 0 0 0 0 Reserved 0 0 0 1 SPECIAL17 0 0 1 X Reserved 0 1 0 0 VRH 0 1 0 1 VRL 0 1 1 0 VRH VRL 2 0 1 1 1 Reserved 1 X X X Reserved Table 10 15 Analog Input Channel Select Cod...

Page 332: ...tional active edges are detected while a conversion sequence is in process the overrun flag is set This flag is cleared when one of the following occurs A Write 1 to ETORF B Write to ATDCTL0 1 2 3 4 A...

Page 333: ...sion clears the conversion counter even if FIFO 1 Module Base 0x0008 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 CMPE 11 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure...

Page 334: ...in a sequence is complete and the result is available in ATDDR5 and so forth If automatic compare of conversion results is enabled CMPE n 1 in ATDCMPE the conversion complete flag is only set if compa...

Page 335: ...input buffer on ANx pin Note Setting this bit will enable the corresponding digital input buffer continuously If this bit is set while simultaneously using it as an analog port there is potentially i...

Page 336: ...this case avoid writing to ATDDRn except for initial values because an A D result might be overwritten 10 3 2 12 1 Left Justified Result Data DJM 0 10 3 2 12 2 Right Justified Result Data DJM 1 Module...

Page 337: ...is always done using all 12 bits of both the conversion result and the compare value in ATDDRn Table 10 21 Conversion result mapping to ATDDRn A D resolution DJM conversion result mapping to ATDDRn 8...

Page 338: ...e 10 4 1 3 Analog to Digital A D Machine The A D Machine performs analog to digital conversions The resolution is program selectable at either 8 or 10 or 12 bits The A D machine uses a successive appr...

Page 339: ...nd sampled as analog channels to the A D converter The analog digital multiplex operation is performed in the input pads The input pad is always connected to the analog input channels of the ADC12B12C...

Page 340: ...2C are listed in Table 10 23 Refer to MCU specification for related vector address and priority See Section 10 3 2 Register Descriptions for further details Table 10 23 ATD Interrupt Vectors Interrupt...

Page 341: ...t Though not exclusively intended for automotive applications CAN protocol is designed to meet the specific requirements of a vehicle serial data bus real time processing reliable operation in the EMI...

Page 342: ...quence SOF Start of Frame CPU bus CPU related read write data bus CAN bus CAN protocol related serial bus oscillator clock Direct clock from external oscillator bus clock CPU bus related clock CAN clo...

Page 343: ...y with integrated low pass filter Programmable loopback mode supports self test operation Programmable listen only mode for monitoring of CAN bus Programmable bus off recovery functionality Separate s...

Page 344: ...pin 11 2 2 TXCAN CAN Transmitter Output Pin TXCAN is the MSCAN transmitter output pin The TXCAN output pin represents the logic level on the CAN bus 0 Dominant state 1 Recessive state 11 2 3 CAN Syste...

Page 345: ...s results from the addition of base address and address offset The base address is determined at the MCU level and can be found in the MCU memory map description The address offset is defined at the m...

Page 346: ...0 TSTAT1 TSTAT0 OVRIF RXF W 0x0005 CANRIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0006 CANTFLG R 0 0 0 0 0 TXE2 TXE1 TXE0 W 0x0007 CANTIER R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W 0x0...

Page 347: ...below 0x000F CANTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W 0x0010 0x0013 CANIDAR0 3 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x0014 0x0017 CANIDMRx R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0...

Page 348: ...ait Mode Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module 0 The module is not affected during wait mode 1 The...

Page 349: ...counters are not affected by initialization mode When this bit is cleared by the CPU the MSCAN restarts and then tries to synchronize to the CAN bus If the MSCAN is not in bus off state it synchroniz...

Page 350: ...age received from a remote node In this state the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message Both transmit and rece...

Page 351: ...BTR0 CANBTR1 CANIDAC CANIDAR0 CANIDAR7 and CANIDMR0 CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode 0 Running The MSCAN operates normally 1 Initialization mode active...

Page 352: ...the number of CAN bus samples taken per bit time 0 One sample per bit 1 Three samples per bit 1 If SAMP 0 the resulting bit value is equal to the value of the single bit positioned at the sample poin...

Page 353: ...G20 Time Segment 2 0 0 0 1 Tq clock cycle 1 1 This setting is not valid Please refer to Table 11 37 for valid settings 0 0 1 2 Tq clock cycles 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles Table 11...

Page 354: ...bus status see Section 11 3 2 6 MSCAN Receiver Interrupt Enable Register CANRIER If not masked an error interrupt is pending while this flag is set CSCIF provides a blocking interrupt That guarantees...

Page 355: ...fer in the receiver FIFO the RXF flag must be cleared to release the buffer A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer RxFG If not masked a receive interru...

Page 356: ...ate changes for generating CSCIF interrupt 11 Generate CSCIF interrupt on all state changes 2 Bus off state is only defined for transmitters by the CAN standard see Bosch CAN 2 0A B protocol specifica...

Page 357: ...s the flag after the message is sent successfully The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request see Section 11 3 2 9 MSCAN Tran...

Page 358: ...ilable for transmission event causes a transmitter empty interrupt request Module Base 0x0008 Access User read write 1 1 Read Anytime Write Anytime when not in initialization mode 7 6 5 4 3 2 1 0 R 0...

Page 359: ...eset 0 0 0 0 0 0 0 0 Unimplemented Figure 11 13 MSCAN Transmitter Message Abort Acknowledge Register CANTAAK Table 11 16 CANTAAK Register Field Descriptions Field Description 2 0 ABTAK 2 0 Abort Ackno...

Page 360: ...n is 0b0000_0110 LDAA CANTBSEL value read is 0b0000_0010 If all transmit message buffers are deselected no accesses are allowed to the CANTXFG registers 11 3 2 12 MSCAN Identifier Acceptance Control R...

Page 361: ...er Acceptance Filter Table 11 19 summarizes the different settings In filter closed mode no message is accepted such that the foreground buffer is never reloaded 2 0 IDHIT 2 0 Identifier Acceptance Hi...

Page 362: ...et 0 0 0 0 0 0 0 0 Unimplemented Figure 11 16 MSCAN Reserved Register Module Base 0x000D Access User read write 1 1 Read Anytime Write Anytime write of 1 clears flag write of 0 ignored 7 6 5 4 3 2 1 0...

Page 363: ...th dual CPUs this may result in a CPU fault condition Writing to this register when in special modes can alter the MSCAN functionality Module Base 0x000E Access User read write 1 1 Read Only when in s...

Page 364: ...re applied Module Base 0x0010 to Module Base 0x0013 Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 7 6 5 4 3 2 1 0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0...

Page 365: ...g identifier mask register Module Base 0x0014 to Module Base 0x0017 Access User read write 1 1 Read Anytime Write Anytime in initialization mode INITRQ 1 and INITAK 1 7 6 5 4 3 2 1 0 R AM7 AM6 AM5 AM4...

Page 366: ...is only available for transmit and receiver buffers if the TIME bit is set see Section 11 3 2 1 MSCAN Control Register 0 CANCTL0 The time stamp register is written by the MSCAN The CPU can only read t...

Page 367: ...Register Access 0x00X0 Identifier Register 0 R W 0x00X1 Identifier Register 1 R W 0x00X2 Identifier Register 2 R W 0x00X3 Identifier Register 3 R W 0x00X4 Data Segment Register 0 R W 0x00X5 Data Segm...

Page 368: ...D14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W 0x00X3 IDR3 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W 0x00X4 DSR0 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X5 DSR1 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W 0x00X6 DSR2 R DB7...

Page 369: ...ection 11 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Unimplemented for receive buffers Reset Undefined because of RAM based implementation 11 3 3 1 Identifier Registers IDR0 IDR3 The ide...

Page 370: ...ifiers consist of 29 bits ID 28 0 for the extended format ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure The priority of an identifier is def...

Page 371: ...D2 ID1 ID0 RTR W Reset x x x x x x x x Figure 11 29 Identifier Register 3 IDR3 Extended Identifier Mapping Table 11 30 IDR3 Register Field Descriptions Extended Field Description 7 1 ID 6 0 Extended F...

Page 372: ...0 Standard Format Identifier The identifiers consist of 11 bits ID 10 0 for the standard format ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedu...

Page 373: ...0x00X2 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always read x Figure 11 32 Identifier Register 2 Standard Mapping Module Base 0x00X3 7 6 5 4 3 2 1 0 R W Reset x x x x x x x x Unused always re...

Page 374: ...rt of frame is sent Module Base 0x00XC 7 6 5 4 3 2 1 0 R DLC3 DLC2 DLC1 DLC0 W Reset x x x x x x x x Unused always read x Figure 11 35 Data Length Register DLR Extended Identifier Mapping Table 11 34...

Page 375: ...me stamp registers Module Base 0x00XD Access User read write 1 1 Read Anytime when TXEx flag is set see Section 11 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit buffer i...

Page 376: ...see Section 11 3 2 7 MSCAN Transmitter Flag Register CANTFLG and the corresponding transmit buffer is selected in CANTBSEL see Section 11 3 2 11 MSCAN Transmit Buffer Selection Register CANTBSEL Writ...

Page 377: ...provides a complete functional description of the MSCAN 11 4 2 Message Storage Figure 11 39 User Model for Message Buffer Organization MSCAN Rx0 Rx1 CAN Receive Transmit Engine Memory Mapped I O CPU b...

Page 378: ...eady for transmission and the CAN bus would be released At least three transmit buffers are required to meet the first of the above requirements under all circumstances The MSCAN has three transmit bu...

Page 379: ...nnot be aborted the user must request the abort by setting the corresponding abort request bit ABTRQ see Section 11 3 2 9 MSCAN Transmitter Message Abort Request Register CANTARQ The MSCAN then grants...

Page 380: ...ceiver FIFO is being filled but all incoming messages are discarded As soon as a receive buffer in the FIFO is available again new valid messages will be accepted 11 4 3 Identifier Acceptance Filter T...

Page 381: ...er acceptance filters each to be applied to the first 8 bits of the identifier This mode implements eight independent filters for the first 8 bits of a CAN 2 0A B compliant standard identifier or a CA...

Page 382: ...10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CANIDAR0 AM7 AM0 CANIDMR0 AC7 AC0 CANIDAR1 AM7 AM0 CANIDMR1 ID Accepted Filter 0 Hit AC7 AC0 CANI...

Page 383: ...0A B Standard Identifier AC7 AC0 CIDAR3 AM7 AM0 CIDMR3 ID Accepted Filter 3 Hit AC7 AC0 CIDAR2 AM7 AM0 CIDMR2 ID Accepted Filter 2 Hit AC7 AC0 CIDAR1 AM7 AM0 CIDMR1 ID Accepted Filter 1 Hit ID28 ID21...

Page 384: ...to a recessive state when the MSCAN goes into the power down mode or initialization mode see Section 11 4 5 6 MSCAN Power Down Mode and Section 11 4 4 5 MSCAN Initialization Mode The MSCAN enable bit...

Page 385: ...ne time quantum Signal edges are expected to happen within this section Time Segment 1 This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard It can be programmed by setting the par...

Page 386: ...1 4 4 Modes of Operation 11 4 4 1 Normal System Operating Modes The MSCAN module behaves as described within this specification in all normal system operating modes Write restrictions exist for some r...

Page 387: ...N enters initialization mode when it is enabled CANE 1 When entering initialization mode during operation any on going transmission or reception is immediately aborted and synchronization to the CAN b...

Page 388: ...to initialization mode NOTE The CPU cannot clear INITRQ before initialization mode INITRQ 1 and INITAK 1 is active 11 4 5 Low Power Options If the MSCAN is disabled CANE 0 the MSCAN clocks are stopped...

Page 389: ...ation in Stop Mode The STOP instruction puts the MCU in a low power consumption stand by mode In stop mode the MSCAN is set in power down mode regardless of the value of the SLPRQ SLPAK and CSWAI bits...

Page 390: ...iately request sleep mode by setting SLPRQ Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations If sleep mode is active the SLPRQ and SLPA...

Page 391: ...e after sleep mode was exited it continues counting the 128 occurrences of 11 consecutive recessive bits 11 4 5 6 MSCAN Power Down Mode The MSCAN is in power down mode Table 11 38 when CPU is in stop...

Page 392: ...ection 11 3 2 Register Descriptions which details all the registers and their bit fields 11 4 7 Interrupts This section describes all interrupts originated by the MSCAN It documents the enable bits an...

Page 393: ...Status Change The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN As soon as the error counters skip into a critical range Tx Rx warning Tx Rx error bus...

Page 394: ...alization mode 4 Clear INITRQ to leave initialization mode and continue 11 5 2 Bus Off Recovery The bus off recovery is user configurable The bus off state can either be left automatically or on user...

Page 395: ...rating at higher baud rates up to a maximum of clock 20 with reduced bus loading The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitan...

Page 396: ...MC9S12XHY Family Reference Manual Rev 1 01 396 Freescale Semiconductor Acknowledge bit generation detection Bus busy detection General Call Address detection Compliant to ten bit address Downloaded fr...

Page 397: ...al special and emulation modes It has two low power modes wait and stop modes 12 1 3 Block Diagram The block diagram of the IIC module is shown in Figure 12 1 Figure 12 1 IIC Block Diagram In Out Data...

Page 398: ...and registers for the IIC module 12 3 1 Register Descriptions This section consists of register descriptions in address order Each description includes a standard register diagram with an associated...

Page 399: ...specific slave address to be used by the IIC bus module The default mode of IIC bus is slave mode for an address match on the bus 0 Reserved Reserved Bit 0 of the IBAD is reserved for future compatibi...

Page 400: ...ap is used to determine the delay from the falling edge of SCL to SDA changing the SDA hold time IBC7 6 defines the multiplier factor MUL The values of MUL are shown in the Table 12 6 Table 12 4 I Bus...

Page 401: ...on used to generate the SDA Hold value from the IBFD bits is SDA Hold MUL x scl2tap SDA_Tap 1 x tap2tap 3 The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits...

Page 402: ...26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1A 112 17 54 57 1B 128 17 62 65 1C 144 25 70 73 1D 160 25 78 81 1E 192 33 94 97 1F 240 3...

Page 403: ...385 1278 1281 3E 3072 513 1534 1537 3F 3840 513 1918 1921 MUL 2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30...

Page 404: ...78 6D 1280 194 636 642 6E 1536 258 764 770 6F 1920 258 956 962 70 1280 130 636 642 71 1536 130 764 770 72 1792 258 892 898 73 2048 258 1020 1026 74 2304 386 1148 1154 75 2560 386 1276 1282 76 3072 514...

Page 405: ...196 9A 448 68 216 228 9B 512 68 248 260 9C 576 100 280 292 9D 640 100 312 324 9E 768 132 376 388 9F 960 132 472 484 A0 640 68 312 324 A1 768 68 376 388 A2 896 132 440 452 A3 1024 132 504 516 A4 1152 1...

Page 406: ...C Control Register IBCR Read and write anytime B2 3584 516 1784 1796 B3 4096 516 2040 2052 B4 4608 772 2296 2308 B5 5120 772 2552 2564 B6 6144 1028 3064 3076 B7 7680 1028 3832 3844 B8 5120 516 2552 25...

Page 407: ...ged from 0 to 1 a START signal is generated on the bus and the master mode is selected When this bit is changed from 1 to 0 a STOP signal is generated and the operation mode changes from master to sla...

Page 408: ...lid during or immediately following a transfer to the IIC module or from the IIC module 0 Transfer in progress 1 Transfer complete 6 IAAS Addressed as a Slave Bit When its own specific address I bus a...

Page 409: ...ed for future use A read operation on this bit will return 0 2 SRW Slave Read Write When IAAS is set this bit indicates the value of the R W command bit of the calling address sent from the master Thi...

Page 410: ...parts START signal slave address transmission data transfer and STOP signal They are described briefly in the following sections and illustrated in Figure 12 10 Module Base 0x0005 7 6 5 4 3 2 1 0 R G...

Page 411: ...new data transfer each data transfer may contain several bytes of data and brings all slaves out of their idle states Figure 12 11 Start and Stop Conditions CL DA Start Signal Ack Bit 1 2 3 4 5 6 7 8...

Page 412: ...arry sub address information for the slave device Each data byte is 8 bits long Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 12 10 There is on...

Page 413: ...In this case the transition from master to slave mode does not generate a STOP condition Meanwhile a status bit is set by hardware to indicate loss of arbitration 12 4 1 7 Clock Synchronization Becaus...

Page 414: ...byte Figure 12 13 Definition of bits in the first byte The address type is identified by ADTYPE When ADTYPE is 0 7 bit address is applied Reversely the address is 10 bit address Generally there are tw...

Page 415: ...h by S W the IIC hardware does not decode and process the first data byte When one byte transfer is done the received data can be read from IBDR The user can control the procedure by enabling or disab...

Page 416: ...ied IBCR2 should be updated to define the rest bits of address 4 Set the IBEN bit of the IIC bus control register IBCR to enable the IIC interface system 5 Modify the bits of the IIC bus control regis...

Page 417: ...the end of the address cycle the master will always be in transmit mode i e the address is transmitted If master receive mode is required indicated by R W bit in IBDR then the Tx Rx bit should be tog...

Page 418: ...match occurred interrupts resulting from subsequent data transfers will have IAAS cleared A data transfer may now be initiated by writing information to IBDR for slave transmits or dummy reading from...

Page 419: ...the byte during which arbitration was lost An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL 1 and MS SL 0 If one master attempts to start transmission while the bu...

Page 420: ...enerate Stop Signal 2nd Last Byte To Be Read Last Byte To Be Read Arbitration Lost Clear IBAL IAAS 1 IAAS 1 SRW 1 TX RX Set TX Mode Write Data To IBDR Set RX Mode Dummy Read From IBDR ACK From Receive...

Page 421: ...Y Family Reference Manual Rev 1 01 Freescale Semiconductor 421 Caution When IIC is configured as 10 bit address the point of the data array in interrupt routine must be reset after it s addressed Down...

Page 422: ...Inter Integrated Circuit IICV3 Block Description MC9S12XHY Family Reference Manual Rev 1 01 422 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 423: ...ed outputs 13 1 1 Features The PWM block includes these distinctive features Eight independent PWM channels with programmable period and duty cycle Dedicated counter for each PWM channel Programmable...

Page 424: ...as an input for the emergency shutdown feature 13 2 2 PWM6 PWM Channel 6 This pin serves as waveform output of PWM channel 6 Period and Duty Counter Channel 6 Clock Select PWM Clock Period and Duty C...

Page 425: ...end users such as factory test control registers and reserved registers are clearly identified by means of shading the appropriate portions of address maps and register diagrams Notes explaining the...

Page 426: ...PWME2 PWME1 PWME0 W 0x0001 PWMPOL R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W 0x0002 PWMCLK R PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 W 0x0003 PWMPRCLK R 0 PCKB2 PCKB1 PCKB0 0 PCKA2...

Page 427: ...0 0 0 0 0 0 0 0 0x0011 PWMCNT5 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0012 PWMCNT6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0013 PWMCNT7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x0014...

Page 428: ...can be irregular 0x001A PWMPER6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001B PWMPER7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001C PWMDTY0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001D PWMDTY1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001E PWMD...

Page 429: ...1 Pulse width channel 6 is enabled The pulse modulated signal becomes available at PWM output bit6 when its clock source begins its next cycle If CON67 1 then bit has no effect and PWM output line 6 i...

Page 430: ...Channel 1 Enable 0 Pulse width channel 1 is disabled 1 Pulse width channel 1 is enabled The pulse modulated signal becomes available at PWM output bit 1 when its clock source begins its next cycle 0 P...

Page 431: ...Channel 6 Clock Select 0 Clock B is the clock source for PWM channel 6 1 Clock SB is the clock source for PWM channel 6 5 PCLK5 Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PW...

Page 432: ...ne of two clock sources which can be used for channels 2 3 6 or 7 These three bits determine the rate of clock B as shown in Table 13 5 2 0 PCKA 2 0 Prescaler Select for Clock A Clock A is one of two...

Page 433: ...te Anytime There are three control bits for concatenation each of which is used to concatenate a pair of PWM channels into one 16 bit channel When channels 6 and 7are concatenated channel 6 registers...

Page 434: ...der byte Channel 3 output pin is used as the output for this 16 bit PWM bit 3 of port PWMP Channel 3 clock select control bit determines the clock source channel 3 polarity bit determines the polarity...

Page 435: ...d 00 in normal modes Write Unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality 13 3 2 9 PWM Scale A Register PWMSCLA PWMSCLA is the progra...

Page 436: ...viding that by two Clock SB Clock B 2 PWMSCLB NOTE When PWMSCLB 00 PWMSCLB value is considered a full scale value of 256 Clock B is thus divided by 512 Any value written to this register will cause th...

Page 437: ...ction 13 4 2 5 Left Aligned Outputs and Section 13 4 2 6 Center Aligned Outputs for more details When the channel is disabled PWMEx 0 the PWMCNTx register does not count When a channel becomes enabled...

Page 438: ...tly to the latches as well as the buffer NOTE Reads of this register return the most recent value written Reads do not necessarily return the value of the currently active period due to the double buf...

Page 439: ...ot necessarily return the value of the currently active duty due to the double buffering scheme See Section 13 4 2 3 PWM Period and Duty for more information NOTE Depending on the polarity bit the dut...

Page 440: ...PWMRSTRT PWM Restart The PWM can only be restarted if the PWM channel input 7 is de asserted After writing a logic 1 to the PWMRSTRT bit trigger event the PWM channels start running after the corresp...

Page 441: ...e mode by setting the PFRZ bit in the PWMCTL register If this bit is set whenever the MCU is in freeze mode freeze mode signal active the input clock to the prescaler is disabled This is useful for em...

Page 442: ...Clock Clock Select M U X PCLK0 Clock to PWM Ch 0 M U X PCLK2 Clock to PWM Ch 2 M U X PCLK1 Clock to PWM Ch 1 M U X PCLK4 Clock to PWM Ch 4 M U X PCLK5 Clock to PWM Ch 5 M U X PCLK6 Clock to PWM Ch 6...

Page 443: ...writes FF into the PWMSCLA register Clock A for this case will be E divided by 4 A pulse will occur at a rate of once every 255x4 E cycles Passing this through the divide by two circuit produces a cl...

Page 444: ...timer Figure 13 19 PWM Timer Channel Block Diagram 13 4 2 1 PWM Enable Each PWM channel has an enable bit PWMEx to start its waveform output When any of the PWMEx bits are set PWMEx 1 the associated...

Page 445: ...waveform not some variation in between If the channel is not enabled then writes to the period and duty registers will go directly to the latches as well as the buffer A change in duty or period can...

Page 446: ...t set according to the polarity bit NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur The counter is cleared at the end of the effective period see Sec...

Page 447: ...lected clock source frequency for the channel A B SA or SB and divide it by the value in the period register for that channel PWMx Frequency Clock A B SA or SB PWMPERx PWMx Duty Cycle high time as a o...

Page 448: ...down count When the PWM counter decrements and matches the duty register again the output flip flop changes state causing the PWM output to also change state When the PWM counter decrements and reache...

Page 449: ...ake the selected clock source frequency for the channel A B SA or SB and divide it by twice the value in the period register for that channel PWMx Frequency Clock A B SA or SB 2 PWMPERx PWMx Duty Cycl...

Page 450: ...hese bits only when both corresponding channels are disabled When channels 6 and 7 are concatenated channel 6 registers become the high order bytes of the double byte channel as shown in Figure 13 24...

Page 451: ...output is disabled In concatenated mode writes to the 16 bit counter by using a 16 bit access or writes to either the low or high order byte of the counter will reset the 16 bit counter Reads of the 1...

Page 452: ...details the registers and their bit fields All special functions or modes which are initialized during or just following reset are described within this section The 8 bit up down counter is configure...

Page 453: ...nges while PWM7ENA 1 or when PWMENA is being asserted while the level at PWM7 is active In stop mode or wait mode with the PSWAI bit set the emergency shutdown feature will drive the PWM outputs to th...

Page 454: ...Pulse Width Modulator S12PWM8B8CV1 MC9S12XHY Family Reference Manual Rev 1 01 454 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 455: ...Local Interconnect Network LSB Least Significant Bit MSB Most Significant Bit NRZ Non Return to Zero RZI Return to Zero Inverted RXD Receive Pin SCI Serial Communication Interface TXD Transmit Pin Tab...

Page 456: ...eiver Programmable transmitter output parity Two receiver wakeup methods Idle line wakeup Address mark wakeup Interrupt driven operation with eight flags Transmitter empty Transmission complete Receiv...

Page 457: ...gure 14 1 SCI Block Diagram SCI Data Register RXD Data In Data Out TXD Receive Shift Register Infrared Decoder Receive Wakeup Control Data Format Control Transmit Control Baud Rate Generator Bus Clock...

Page 458: ...nfrared data An idle line is detected as a line high This input is ignored when the receiver is disabled and should be terminated to a known voltage 14 3 Memory Map and Register Definition This sectio...

Page 459: ...BR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0002 SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0000 SCIASR12 R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W 0x0001 SCIACR12 R RXEDGIE 0 0 0 0 0 BERRIE BKDIE...

Page 460: ...d Descriptions Field Description 7 IREN Infrared Enable Bit This bit enables disables the infrared modulation demodulation submodule 0 IR disabled 1 IR enabled 6 5 TNP 1 0 Transmitter Narrow Pulse Bit...

Page 461: ...be enabled to use the loop function 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit 6 SCISWAI SCI Stop in Wait Mode Bit SCISWAI disables the SCI in...

Page 462: ...ity Enable Bit PE enables the parity function When enabled the parity function inserts a parity bit in the most significant bit position 0 Parity function disabled 1 Parity function enabled 0 PT Parit...

Page 463: ...the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened The value is only meaningful if BERRIF 1 0 A low input was sampled when a high...

Page 464: ...Input Active Edge Interrupt Enable RXEDGIE enables the receive input active edge interrupt flag RXEDGIF to generate interrupt requests 0 RXEDGIF interrupt requests disabled 1 RXEDGIF interrupt reques...

Page 465: ...2 1 BERRM 1 0 Bit Error Mode Those two bits determines the functionality of the bit error detect feature See Table 14 9 0 BKDFE Break Detect Feature Enable BKDFE enables the break detect circuitry 0...

Page 466: ...errupt requests enabled 4 ILIE Idle Line Interrupt Enable Bit ILIE enables the idle line flag IDLE to generate interrupt requests 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled 3...

Page 467: ...set low when there is a transmission in progress or when a preamble or break character is loaded TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted W...

Page 468: ...nt 2 or any time after When this happens a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received 2 NF Noise Flag NF is set when the SCI detects...

Page 469: ...r a one for inverted polarity 0 Normal polarity 1 Inverted polarity 3 RXPOL Receive Polarity This bit control the polarity of the received data In NRZ format a one is represented by a mark and a zero...

Page 470: ...gh SCIDRH then SCIDRL Module Base 0x0006 7 6 5 4 3 2 1 0 R R8 T8 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 14 12 SCI Data Registers SCIDRH Module Base 0x0007 7 6 5 4 3 2 1 0...

Page 471: ...itors the status of the SCI writes the data to be transmitted and processes received data Figure 14 14 Detailed SCI Block Diagram SCI Data Receive Shift Register SCI Data Register Transmit Shift Regis...

Page 472: ...ed block receives two clock sources from the SCI R16XCLK and R32XCLK which are configured to generate the narrow pulse width during transmission The R16XCLK and R32XCLK are internal clocks with freque...

Page 473: ...e ninth data bit is the T8 bit in SCI data register high SCIDRH It remains unchanged after transmission and can be used repeatedly without rewriting it A frame with nine data bits has a total of 11 bi...

Page 474: ...e Baud rate generation is subject to one source of error Integer division of the bus clock may not give the exact target frequency Table 14 16 lists some examples of achieving target baud rates with a...

Page 475: ...are transferred to the transmitter shift register The transmit shift register then shifts a frame out through the TXD pin after it has prefaced them with a start bit and appended them with a stop bit...

Page 476: ...itten to the T8 bit in SCIDRH if the SCI is in 9 bit data format A new transmission will not result until the TDRE flag has been cleared 3 Repeat step 2 for each subsequent transmission NOTE The TDRE...

Page 477: ...ntrol register 1 SCICR1 As long as SBK is at logic 1 transmitter logic continuously loads break characters into the transmit shift register After software clears the SBK bit the shift register finishe...

Page 478: ...arity bit Idle character length depends on the M bit in SCI control register 1 SCICR1 The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE b...

Page 479: ...is discarded the transmit data register empty and the transmission complete flag will be set The bit error interrupt flag BERRIF will be set No further transmissions will take place until the BERRIF...

Page 480: ...s the read only buffer between the internal data bus and the receive shift register After a complete frame shifts into the receive shift register the data portion of the frame transfers to the SCI dat...

Page 481: ...ogic does an asynchronous search for a logic 0 preceded by three logic 1s When the falling edge of a possible start bit occurs the RT clock begins to count to 16 Figure 14 21 Receiver Data Sampling To...

Page 482: ...ccessful start bit verification the noise flag NF is set and the receiver assumes that the bit is a start bit logic 0 To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 a...

Page 483: ...s the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful Figure 14 23 Start Bit Search Example 2 Reset R...

Page 484: ...e early in the start bit time Although this noise does not affect proper synchronization with the start bit time it does set the noise flag Figure 14 25 Start Bit Search Example 4 Reset RT Clock RT1 R...

Page 485: ...nored Figure 14 27 Start Bit Search Example 6 14 4 6 4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame it sets the framing error f...

Page 486: ...it data samples at RT8 RT9 and RT10 Figure 14 28 Slow Data Let s take RTr as receiver RT clock and RTt as transmitter RT clock For an 8 bit data character it takes the receiver 9 bit times x 16 RTr cy...

Page 487: ...r cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles 176 RTt cycles The maximum percent difference between the receiver count and the transmitter count of a...

Page 488: ...Mark Wakeup WAKE 1 In this wakeup method a logic 1 in the most significant bit MSB position of a frame clears the RWU bit and wakes up the SCI The logic 1 in the MSB position marks a frame as an addr...

Page 489: ...utput goes to the receiver input The RXD pin is disconnected from the SCI Figure 14 31 Loop Operation LOOPS 1 RSRC 0 Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI con...

Page 490: ...reception in progress and resets the SCI The receive input active edge detect circuit is still active in stop mode An active edge on the receive input can be used to bring the CPU out of stop mode 14...

Page 491: ...ansmission in progress TC is set high when the TDRE flag is set and no data preamble or break character is being transmitted When TC is set the TXD pin becomes idle logic 1 Clear TC by reading SCI sta...

Page 492: ...ion like LIN was detected Clear BERRIF by writing a 1 to the SCIASR1 SCI alternative status register 1 This flag is also cleared if the bit error detect feature is disabled 14 5 3 1 8 BKDIF Descriptio...

Page 493: ...Selectable 8 or 16 bit transfer width Bidirectional mode Slave select output Mode fault error flag with CPU interrupt capability Double buffered data register Serial clock with programmable polarity...

Page 494: ...nsmission of data continues so that the slave stays synchronized to the master Stop mode The SPI is inactive in stop mode for reduced power consumption If the SPI is configured as a master any transmi...

Page 495: ...Pin This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master SPI Control Register 1 SPI Control Register 2 SPI Baud Ra...

Page 496: ...The memory map for the SPI is given in Figure 15 2 The address listed for each register is the sum of a base address and an address offset The base address is defined at the SoC level and the address...

Page 497: ...er consumption 1 SPI enabled port pins are dedicated to SPI functions 5 SPTIE SPI Transmit Interrupt Enable This bit enables SPI interrupt requests if SPTEF flag is set 0 SPTEF interrupt disabled 1 SP...

Page 498: ...tes of the data register always have the MSB in the highest bit position In master mode a change of this bit will abort a transmission in progress and force the SPI system into idle state 0 Data is tr...

Page 499: ...ange of this bit will abort a transmission in progress and force the SPI system into idle state 0 SS port pin is not used by the SPI 1 SS port pin with MODF feature 3 BIDIROE Output Enable in the Bidi...

Page 500: ...2 0 SPI Baud Rate Preselection Bits These bits specify the SPI baud rates as shown in Table 15 6 In master mode a change of these bits will abort a transmission in progress and force the SPI system in...

Page 501: ...1 1 1 1 1 1024 24 41 kbit s 1 0 0 0 0 0 10 2 5 Mbit s 1 0 0 0 0 1 20 1 25 Mbit s 1 0 0 0 1 0 40 625 kbit s 1 0 0 0 1 1 80 312 5 kbit s 1 0 0 1 0 0 160 156 25 kbit s 1 0 0 1 0 1 320 78 13 kbit s 1 0 0...

Page 502: ...IF Flag please refer to Table 15 8 0 Transfer not yet complete 1 New data copied to SPIDR 5 SPTEF SPI Transmit Empty Interrupt Flag If set this bit indicates that the transmit data register is empty F...

Page 503: ...lag is cleared only by the read of SPIDRL after reading SPISR with SPIF 1 Byte Read SPIDRL or Word Read SPIDRH SPIDRL XFRW Bit SPTEF Interrupt Flag Clearing Sequence 0 Read SPISR with SPTEF 1 then Wri...

Page 504: ...second data value has been received the second received data is kept as valid data in the receive shift register until the start of another transmission The data in the SPIDR does not change If SPIF i...

Page 505: ...the SPI enable SPE bit in SPI control register 1 While SPE is set the four associated SPI port pins are dedicated to the SPI function as Slave select SS Serial clock SCK Master out slave in MOSI Mast...

Page 506: ...data on odd numbered SCK edges or on even numbered SCK edges see Section 15 4 3 Transmission Formats The SPI can be configured to operate as a master or as a slave When the MSTR bit in SPI control reg...

Page 507: ...OL CPHA SSOE LSBFE XFRW MODFEN SPC0 or BIDIROE with SPC0 set SPPR2 SPPR0 and SPR2 SPR0 in master mode will abort a transmission in progress and force the SPI into idle state The remote slave cannot de...

Page 508: ...sed to get the first data bit onto the serial data output pin When CPHA is clear and the SS input is low slave selected the first bit of the SPI data is driven out of the serial data output pin After...

Page 509: ...t pin is shifted into the LSB or MSB of the shift register depending on LSBFE bit After this second edge the next bit of the SPI master data is transmitted out of the serial data output pin of the mas...

Page 510: ...3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS I MOSI pin MISO pin Master only MOSI MISO tT If next transfer begins here for tT tl tL Minimum 1 2 SCK tI tL tL Minimum leading time before the first SC...

Page 511: ...ter the half SCK clock cycle synchronization delay This first edge commands the slave to transfer its first data bit to the serial data input pin of the master A half SCK cycle later the second edge a...

Page 512: ...shows two clocking variations for CPHA 1 The diagram may be interpreted as a master or slave timing diagram because the SCK MISO and MOSI pins are connected directly between the master and the slave T...

Page 513: ...k which results in the SPI baud rate The SPI clock rate is determined by the product of the value in the baud rate preselection bits SPPR2 SPPR0 and the value in the baud rate selection bits SPR2 SPR0...

Page 514: ...tricals chapter of this data sheet 15 4 5 Special Features 15 4 5 1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it hig...

Page 515: ...he SPI and MOSI is not used This must be considered if the MISO pin is used for another purpose 15 4 6 Error Conditions The SPI has one error condition Mode fault error 15 4 6 1 Mode Fault Error If th...

Page 516: ...in Run Mode In run mode with the SPI system enable SPE bit in the SPI control register clear the SPI system is in a low power disabled state SPI registers remain accessible but clocks to the core of t...

Page 517: ...e master The stop mode is not dependent on the SPISWAI bit 15 4 7 4 Reset The reset values of registers and signals are described in Section 15 3 Memory Map and Register Definition which details the r...

Page 518: ...ar until it is serviced SPIF has an automatic clearing process which is described in Section 15 3 2 4 SPI Status Register SPISR 15 4 7 5 3 SPTEF SPTEF occurs when the SPI data register is ready to acc...

Page 519: ...53 5 16 3 2 13 16 53 5 16 3 2 15 16 53 7 16 3 2 16 16 53 8 16 3 2 19 16 54 0 16 4 2 16 543 16 4 3 16 543 Revised flag clearing procedure whereby TEN or PAEN bit must be set when clearing flags Add fom...

Page 520: ...time accumulator The pulse accumulator shares timer channel 7 when in event mode A full access for the counter registers or the input capture output compare registers should take place in one clock c...

Page 521: ...OC7 PA input interrupt PA overflow interrupt Timer overflow interrupt Timer channel 0 interrupt Timer channel 7 interrupt Registers Bus clock Input capture Output compare Input capture Output compare...

Page 522: ...agram Figure 16 3 Interrupt Flag Setting Edge detector Intermodule Bus PT7 M clock Divide by 64 Clock select CLK0 CLK1 4 1 MUX TIMCLK PACLK PACLK 256 PACLK 65536 Prescaled clock PCLK Timer clock Inter...

Page 523: ...6 Pin This pin serves as input capture or output compare for channel 6 16 2 3 IOC5 Input Capture and Output Compare Channel 5 Pin This pin serves as input capture or output compare for channel 5 16 2...

Page 524: ...s the sum of the base address for the TIM16B8CV2 module and the address offset for each register 16 3 2 Register Descriptions This section consists of register descriptions in address order Each descr...

Page 525: ...R TOI 0 0 0 TCRE PR2 PR1 PR0 W 0x000E TFLG1 R C7F C6F C5F C4F C3F C2F C1F C0F W 0x000F TFLG2 R TOF 0 0 0 0 0 0 0 W 0x0010 0x001F TCxH TCxL R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W R...

Page 526: ...2 IOS1 IOS0 W Reset 0 0 0 0 0 0 0 0 Figure 16 6 Timer Input Capture Output Compare Select TIOS Table 16 2 TIOS Field Descriptions Field Description 7 0 IOS 7 0 Input Capture or Output Compare Channel...

Page 527: ...orced output compare action will take precedence and interrupt flag won t get set Module Base 0x0002 7 6 5 4 3 2 1 0 R OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 W Reset 0 0 0 0 0 0 0 0 Figure 16...

Page 528: ...e 16 9 Output Compare 7 Data Register OC7D Table 16 5 OC7D Field Descriptions Field Description 7 0 OC7D 7 0 Output Compare 7 Data A channel 7 event which can be a counter overflow when TTOV 7 is set...

Page 529: ...on 7 TEN Timer Enable 0 Disables the main timer including the counter Can be used for reducing power consumption 1 Allows the timer to function normally If for any reason the timer is not active there...

Page 530: ...ed accesses 3 PRNT Precision Timer 0 Enables legacy timer PR0 PR1 and PR2 bits of the TSCR2 register are used for timer counter prescaler selection 1 Enables precision timer All bits of the PTPSR regi...

Page 531: ...r OLx is 1 the pin associated with OCx becomes an output tied to OCx Note To enable output action by OMx bits on timer port the corresponding bit in OC7M should be cleared For an output line to be dri...

Page 532: ...ure Output Compare register IOCx is channel x OMx OLx is the register TCTL1 TCTL2 OC7Dx is the register OC7D bit x IOCx OC7Dx OMx OLx means that both OC7 event and OCx event will change channel x valu...

Page 533: ...on 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge rising or falling Module Base 0x000C 7 6 5 4 3 2 1 0 R C7I C6I C5I C4I C3I C2I C1I C0...

Page 534: ...an up counting modulus counter 0 Counter reset inhibited and counter free runs 1 Counter reset by a successful output compare 7 Note If TC7 0x0000 and TCRE 1 TCNT will stay at 0x0000 continuously If T...

Page 535: ...esponding bits to be cleared Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set Module Base 0x000E 7 6 5 4 3 2 1 0 R C7F C6F C5F C4F C3F C2F C1F C0F W Reset 0 0 0 0...

Page 536: ...it will give a different result Table 16 17 TRLG2 Field Descriptions Field Description 7 TOF Timer Overflow Flag Set when 16 bit free running timer overflows from 0xFFFF to 0x0000 Clearing this bit re...

Page 537: ...umulator is enabled PAEN 1 See Table 16 19 0 Event counter mode 1 Gated time accumulation mode 4 PEDGE Pulse Accumulator Edge Control This bit is active only when the Pulse Accumulator is enabled PAEN...

Page 538: ...r is set any access to the PACNT register will clear all the flags in the PAFLG register Timer module or Pulse Accumulator must stay enabled TEN 1 or PAEN 1 while clearing these bits Table 16 19 Pin A...

Page 539: ...from 0xFFFF to 0x0000 Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one 0 PAIF Pulse Accumulator Input edge...

Page 540: ...pare Pin Disconnect Register OCPD Table 16 22 OCPD Field Description Field Description OCPD 7 0 Output Compare Pin Disconnect Bits 0 Enables the timer channel port Ouptut Compare action will occur on...

Page 541: ...iption 7 0 PTPS 7 0 Precision Timer Prescaler Select Bits These eight bits specify the division rate of the main Timer prescaler These are effective only when the PRNT bit of TSCR1 is set to 1 Table 1...

Page 542: ...TOR TCNT hi TCNT lo CHANNEL 1 TC1 16 BIT COMPARATOR 16 BIT COUNTER INTERRUPT LOGIC TOF TOI C0F C1F EDGE DETECT IOC1 PIN LOGIC EDGE DETECT CxF CHANNEL7 TC7 16 BIT COMPARATOR C7F IOC7 PIN LOGIC EDGE DET...

Page 543: ...uency When the timer counter reaches the value in the channel registers of an output compare channel the timer can set clear or toggle the channel pin if the corresponding OCPDx bit is set to zero An...

Page 544: ...ted time accumulation mode Counting pulses from a divide by 64 clock The PAMOD bit selects the mode of operation The minimum pulse width for the PAI input is greater than two bus clocks 16 4 5 Event C...

Page 545: ...timer prescaler generates the divided by 64 clock If the timer is not active there is no divided by 64 clock 16 5 Resets The reset state of each individual bit is listed within Section 16 3 Memory Ma...

Page 546: ...will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller 16 6 3 Pulse Accumulator Overflow Interrupt PAOVF This active high output w...

Page 547: ...generation bias voltage level select frame duty select backplane select and frontplane select enable to produce the required frame frequency and voltage waveforms LCD RAM contains the data to be disp...

Page 548: ...D40F4BV2 module supports five operation modes with different numbers of backplanes and different biasing levels During wait mode the LCD operation can be suspended under software control Depending on...

Page 549: ...conductor 549 Figure 17 1 LCD40F4BV2 Block Diagram LCD RAM 20 bytes Timing and Control Logic Frontplane Drivers Voltage Generator Backplane Drivers Internal Address Data Clocks V3 V2 V1 V0 V3 V2 V1 V0...

Page 550: ...ve supply voltage for the LCD waveform generation 17 3 Memory Map and Register Definition This section provides a detailed description of all memory and registers 17 3 1 Module Memory Map The memory m...

Page 551: ...ocation 0 Read Write 0x0009 LCDRAM Location 1 Read Write 0x000A LCDRAM Location 2 Read Write 0x000B LCDRAM Location 3 Read Write 0x000C LCDRAM Location 4 Read Write 0x000D LCDRAM Location 5 Read Write...

Page 552: ...System Enable The LCDEN bit starts the LCD waveform generator 0 All frontplane and backplane pins are disabled In addition the LCD40F4BV2 system is disabled and all LCD waveform generation clocks are...

Page 553: ...D Control Register 1 LCDCR1 Table 17 5 LCDCR1 Field Descriptions Field Description 1 LCDSWAI LCD Stop in Wait Mode This bit controls the LCD operation while in wait mode 0 LCD operates normally in wai...

Page 554: ...R FP15EN FP14EN FP13EN FP12EN FP11EN FP10EN FP9EN FP8EN W Reset 0 0 0 0 0 0 0 0 Figure 17 5 LCD Frontplane Enable Register 1 FPENR1 Module Base 0x0004 7 6 5 4 3 2 1 0 R FP23EN FP22EN FP21EN FP20EN FP...

Page 555: ...Reset I I I I I I I I 0x0009 R FP3BP3 FP3BP2 FP3BP1 FP3BP0 FP2BP3 FP2BP2 FP2BP1 FP2BP0 LCDRAM W Reset I I I I I I I I 0x000A R FP5BP3 FP5BP2 FP5BP1 FP5BP0 FP4BP3 FP4BP2 FP4BP1 FP4BP0 LCDRAM W Reset I...

Page 556: ...26BP3 FP26BP2 FP26BP1 FP26BP0 LCDRAM W Reset I I I I I I I I 0x0016 R FP29BP3 FP29BP2 FP29BP1 FP29BP0 FP28BP3 FP28BP2 FP28BP1 FP28BP0 LCDRAM W Reset I I I I I I I I 0x0017 R FP31BP3 FP31BP2 FP31BP1 FP...

Page 557: ...ck IRCCLK and divider determine the LCD clock frequency The divider is set by the LCD clock prescaler bits LCLK 2 0 in the LCD control register 0 LCDCR0 Table 17 8 shows the LCD clock and frame freque...

Page 558: ...crolling purposes When LCDEN 0 the LCD RAM can be used as on chip RAM Writing or reading of the LCDEN bit does not change the contents of the LCD RAM After a reset the LCD RAM contents will be indeter...

Page 559: ...purpose I O ports 17 4 2 Operation in Wait Mode The LCD40F4BV2 driver system operation during wait mode is controlled by the LCD stop in wait LCDSWAI bit in the LCD control register 1 LCDCR1 If LCDSWA...

Page 560: ...Reference Manual Rev 1 01 560 Freescale Semiconductor 17 4 4 LCD Waveform Examples Figure 17 10 through Figure 17 14 show the timing examples of the LCD output waveforms for the available modes of ope...

Page 561: ...1 1 Bias Mode Duty 1 1 DUTY1 0 DUTY0 1 Bias 1 1 BIAS 0 or BIAS 1 V0 V1 VSSX V2 V3 VLCD BP1 BP2 and BP3 are not used a maximum of 40 segments are displayed Figure 17 10 1 1 Duty and 1 1 Bias 0 0 VLCD V...

Page 562: ...3 are not used a maximum of 80 segments are displayed Figure 17 11 1 2 Duty and 1 2 Bias 0 VLCD VSSX BP0 VLCD VLCD BP0 FPx OFF 1 Frame VLCD 1 2 VLCD VSSX BP1 VLCD VSSX FPx xx10 VLCD VSSX FPy xx00 VLCD...

Page 563: ...1 01 Freescale Semiconductor 563 17 4 4 3 1 2 Duty Multiplexed with 1 3 Bias Mode Duty 1 2 DUTY1 1 DUTY0 0 Bias 1 3 BIAS 1 V0 VSSX V1 VLCD 1 3 V2 VLCD 2 3 V3 VLCD BP2 and BP3 are not used a maximum o...

Page 564: ...SSX BP0 VLCD BP0 FPx OFF 1 Frame VLCD 2 3 VLCD 2 3 VLCD 2 3 VLCD VSSX BP1 VLCD 2 3 VLCD VSSX FPx xx10 VLCD 2 3 VLCD VSSX FPy xx00 VLCD 2 3 VLCD VSSX FPz xx11 VLCD 2 3 VLCD 1 3 VLCD 1 3 0 VLCD VLCD BP1...

Page 565: ...1 3 V2 VLCD 2 3 V3 VLCD BP3 is not used a maximum of 120 segments are displayed Figure 17 13 1 3 Duty and 1 3 Bias VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 0 VLCD VSSX...

Page 566: ...VLCD 2 3 V3 VLCD A maximum of 160 segments are displayed Figure 17 14 1 4 Duty and 1 3 Bias VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 VLCD 1 3 0 VLCD VSSX BP0 VLCD VLCD B...

Page 567: ...The reset values of registers and signals are described in Section 17 3 Memory Map and Register Definition The behavior of the LCD40F4BV2 system during reset is described in Section 17 4 1 LCD Driver...

Page 568: ...Liquid Crystal Display LCD40F4BV2 Block Description MC9S12XHY Family Reference Manual Rev 1 01 568 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 569: ...ts within a Flash word or phrase is not allowed The Flash memory may be read as bytes aligned words or misaligned words Read access time is one bus cycle for bytes and aligned words and two bus cycles...

Page 570: ...gram Once field The Program IFR is visible in the global memory map by setting the PGMIFRON bit in the MMCCTL1 register 18 1 2 Features 18 1 2 1 P Flash Features 256 Kbytes of P Flash memory composed...

Page 571: ...nauthorized access to the Flash memory 18 1 3 Block Diagram The block diagram of the Flash module is shown in Figure 18 1 Figure 18 1 FTMR256K1 Block Diagram Oscillator Clock Divider Clock XTAL Comman...

Page 572: ...ddresses in the Flash memory can be activated for protection The Flash memory addresses covered by these protectable regions are shown in the P Flash memory map The higher address region is mainly tar...

Page 573: ...ister FSEC 1 Older versions may have swapped protection byte addresses 2 0x7FF08 0x7F_FF0F form a Flash phrase and must be programmed in a single command write sequence Each byte in the 0x7F_FF08 0x7F...

Page 574: ...wer Region 1 2 4 8 Kbytes 0x7F_8000 0x7F_9000 0x7F_8400 0x7F_8800 0x7F_A000 P Flash END 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protecte...

Page 575: ...Flash register contents and Memory Controller behavior Table 18 3 Program IFR Fields Global Address PGMIFRON Size Bytes Field Description 0x40_0000 0x40_0007 8 Device ID 0x40_0008 0x40_00E7 224 Reserv...

Page 576: ...0 IGNSF 0 0 FDFD FSFD W 0x0005 FERCNFG R 0 DFDIE SFDIE W 0x0006 FSTAT R CCIF 0 ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 W 0x0007 FERSTAT R 0 0 0 0 0 0 DFDIF SFDIF W 0x0008 FPROT R FPOPEN RNV6 FPHDIS...

Page 577: ...ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x000F FECCRLO R ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0 W 0x0010 FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x0011 FRSV2 R 0 0 0 0 0 0 0 0 W 0x0012 FRSV3 R 0...

Page 578: ...der Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divide OSCCLK down to ge...

Page 579: ...x24 6 30 7 35 0x06 38 85 39 90 0x25 7 35 8 40 0x07 39 90 40 95 0x26 8 40 9 45 0x08 40 95 42 00 0x27 9 45 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A...

Page 580: ...dule Base 0x0001 7 6 5 4 3 2 1 0 R KEYEN 1 0 RNV 5 2 SEC 1 0 W Reset F F F F F F F F Unimplemented or Reserved Figure 18 5 Flash Security Register FSEC Table 18 6 FSEC Field Descriptions Field Descrip...

Page 581: ...4 3 2 1 0 R 0 0 0 0 0 CCOBIX 2 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 18 6 FCCOB Index Register FCCOBIX Table 18 9 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Commo...

Page 582: ...ot be generated 1 FDFD Force Double Bit Fault Detect The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine The FDFD...

Page 583: ...IE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set...

Page 584: ...ess error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P Flash or D Flas...

Page 585: ...he FSTAT register The block erase of a P Flash block is not possible if any of the P Flash sectors contained in the same P Flash block are protected Table 18 14 FERSTAT Field Descriptions Field Descri...

Page 586: ...d unprotected area in P Flash memory as shown inTable 18 17 The FPHS bits can only be written to while the FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determ...

Page 587: ...t can be changed by the user The P Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is no...

Page 588: ...0 FPLS 1 0 FPHDIS 1 FPLDIS 1 FPHDIS 1 FPLDIS 0 FPHDIS 0 FPLDIS 1 FPHDIS 0 FPLDIS 0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined...

Page 589: ...to 0 protection enabled If the DPOPEN bit is set the state of the DPS bits is irrelevant During the reset sequence the DFPROT register is loaded with the contents of the D Flash protection byte in th...

Page 590: ...ine the size of the protected area in the D Flash memory as shown in Table 18 21 Table 18 21 D Flash Protection Address Range DPS 4 0 Global Address Range Protected Size 0_0000 0x10_0000 0x10_00FF 256...

Page 591: ...n the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes 1_0110 0x10_0000 0x10_16FF 5888 bytes 1_0111 0x10_0000 0x10_17FF 6144 bytes 1_1...

Page 592: ...ommand code followed by the parameters for this specific Flash command For details on the FCCOB settings required by each command see the Flash command descriptions in Section 18 4 2 18 3 1 12 Flash R...

Page 593: ...ored no other fault information will be recorded until the specific ECC fault flag has been cleared In the event of simultaneous ECC faults the priority for fault recording is double bit fault over si...

Page 594: ...tings ECCRIX 2 0 FECCR Register Content Bits 15 8 Bit 7 Bits 6 0 000 Parity bits read from Flash block 0 Global address 22 16 001 Global address 15 0 010 Data 0 15 0 011 Data 1 15 0 P Flash only 100 D...

Page 595: ...ster read 0 and are not writable 18 3 1 17 Flash Reserved3 Register FRSV3 This Flash register is reserved for factory testing All bits in the FRSV3 register read 0 and are not writable 18 3 1 18 Flash...

Page 596: ...after a reset the user is required to write the FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz Table 18 5 shows recommended values for the FDIV field based on OSCCLK frequency NOTE...

Page 597: ...d CAUTION Writes to any Flash register must be avoided while a Flash command is active CCIF 0 to prevent corruption of Flash register contents and Memory Controller behavior 18 4 1 2 1 Define FCCOB Co...

Page 598: ...lation Read FSTAT register Read FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no B...

Page 599: ...SS3 3 Unsecured Special Single Chip mode ST4 4 Unsecured Special Mode NS5 5 Secured Normal Single Chip mode NX6 6 Secured Normal Expanded mode SS7 7 Secured Special Single Chip mode ST8 8 Secured Spec...

Page 600: ...Erase a P Flash or D Flash block An erase of the full P Flash block is only possible when FPLDIS FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command 0x0A Erase P Flash...

Page 601: ...l 0 If the ACCERR or FPVIOL bits are set in the FSTAT register the user must clear these bits before starting any command write sequence see Section 18 3 1 7 CAUTION A Flash word or phrase must be in...

Page 602: ...n the P Flash memory is erased The Erase Verify P Flash Section command defines the starting point of the code to be verified and the number of phrases The section to be verified cannot cross a 256 Kb...

Page 603: ...n has completed Valid Table 18 33 Erase Verify P Flash Section Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x03 Global address 22 16 of a P Flash block 001 Global address 15 0 of the fi...

Page 604: ...ess and will then proceed to verify the data words read back as expected The CCIF flag will set after the Program P Flash operation has completed Table 18 36 Read Once Command Error Handling Register...

Page 605: ...d by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed Valid phrase index values for the Program Once command range from 0x000...

Page 606: ...mmand launch Set if command not available in current mode see Table 18 26 Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 1 If a Program Once phrase...

Page 607: ...to identify Flash block 001 Global address 15 0 in Flash block to be erased Table 18 44 Erase Flash Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 a...

Page 608: ...ses security if user supplied keys match those stored in the Flash security bytes of the Flash configuration field see Table 18 46 Erase P Flash Sector Command Error Handling Register Error Bit Error...

Page 609: ...d are aborted set ACCERR until a reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has completed 18 4 2 12 Set User Margin Level Command The Set User Margin Level comman...

Page 610: ...ses the Memory Controller to set the margin level specified for future read operations of a specific P Flash or D Flash block Table 18 52 Valid Set User Margin Level Settings CCOB CCOBIX 001 Level Des...

Page 611: ...2 14 Erase Verify D Flash Section Command The Erase Verify D Flash Section command will verify that a section of code in the D Flash is erased The Erase Verify D Flash Section command defines the star...

Page 612: ...obal address 22 16 to identify the D Flash block 001 Global address 15 0 of the first word to be verified 010 Number of words to be verified Table 18 58 Erase Verify D Flash Section Command Error Hand...

Page 613: ...le 18 60 Program D Flash Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if CCOBIX 2 0 101 at command launch Set if command not avail...

Page 614: ...us Register FSTAT and Section 18 3 1 8 Flash Error Status Register FERSTAT The logic used for generating the Flash module interrupts is shown in Figure 18 26 Table 18 62 Erase D Flash Sector Command E...

Page 615: ...Flash configuration field This assumes that you are starting from a mode where the necessary P Flash erase and program commands are available and that the upper region of the P Flash is unprotected I...

Page 616: ...ash security byte can be reprogrammed to the unsecure state if desired In the unsecure state the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00 0x7F_FF07...

Page 617: ...Flash module reverts to built in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence If a double bit fault is...

Page 618: ...256 KByte Flash Module S12XFTMR256K1V1 MC9S12XHY Family Reference Manual Rev 1 01 618 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 619: ...n a Flash word or phrase is not allowed The Flash memory may be read as bytes aligned words or misaligned words Read access time is one bus cycle for bytes and aligned words and two bus cycles for mis...

Page 620: ...visible in the global memory map by setting the PGMIFRON bit in the MMCCTL1 register 19 1 2 Features 19 1 2 1 P Flash Features Single bit fault correction and double bit fault detection within a 64 bi...

Page 621: ...the Flash module Read data from unimplemented memory space in the Flash module is undefined Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash mod...

Page 622: ...ell as security information that allows the MCU to restrict access to the Flash module are stored in the Flash configuration field as described in Table 19 1 Table 19 1 Flash Configuration Field1 1 Ol...

Page 623: ...4 8 Kbytes 0x7F_8000 0x7F_9000 0x7F_8400 0x7F_8800 0x7F_A000 P Flash END 0x7F_FFFF 0x7F_F800 0x7F_F000 0x7F_E000 Flash Protected Unprotected Higher Region 2 4 8 16 Kbytes Flash Protected Unprotected R...

Page 624: ...Flash register contents and Memory Controller behavior Table 19 2 Program IFR Fields Global Address PGMIFRON Size Bytes Field Description 0x40_0000 0x40_0007 8 Device ID 0x40_0008 0x40_00E7 224 Reserv...

Page 625: ...0 IGNSF 0 0 FDFD FSFD W 0x0005 FERCNFG R 0 DFDIE SFDIE W 0x0006 FSTAT R CCIF 0 ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 W 0x0007 FERSTAT R 0 0 0 0 0 0 DFDIF SFDIF W 0x0008 FPROT R FPOPEN RNV6 FPHDIS...

Page 626: ...ECCR12 ECCR11 ECCR10 ECCR9 ECCR8 W 0x000F FECCRLO R ECCR7 ECCR6 ECCR5 ECCR4 ECCR3 ECCR2 ECCR1 ECCR0 W 0x0010 FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W 0x0011 FRSV2 R 0 0 0 0 0 0 0 0 W 0x0012 FRSV3 R 0...

Page 627: ...der Loaded 0 FCLKDIV register has not been written 1 FCLKDIV register has been written since the last reset 6 0 FDIV 6 0 Clock Divider Bits FDIV 6 0 must be set to effectively divide OSCCLK down to ge...

Page 628: ...x24 6 30 7 35 0x06 38 85 39 90 0x25 7 35 8 40 0x07 39 90 40 95 0x26 8 40 9 45 0x08 40 95 42 00 0x27 9 45 10 50 0x09 42 00 43 05 0x28 10 50 11 55 0x0A 43 05 44 10 0x29 11 55 12 60 0x0B 44 10 45 15 0x2A...

Page 629: ...dule Base 0x0001 7 6 5 4 3 2 1 0 R KEYEN 1 0 RNV 5 2 SEC 1 0 W Reset F F F F F F F F Unimplemented or Reserved Figure 19 3 Flash Security Register FSEC Table 19 5 FSEC Field Descriptions Field Descrip...

Page 630: ...4 3 2 1 0 R 0 0 0 0 0 CCOBIX 2 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 19 4 FCCOB Index Register FCCOBIX Table 19 8 FCCOBIX Field Descriptions Field Description 2 0 CCOBIX 1 0 Commo...

Page 631: ...ot be generated 1 FDFD Force Double Bit Fault Detect The FDFD bit allows the user to simulate a double bit fault during Flash array read operations and check the associated interrupt routine The FDFD...

Page 632: ...DIE bit controls interrupt generation when a double bit fault is detected during a Flash block read operation 0 DFDIF interrupt disabled 1 An interrupt will be requested whenever the DFDIF flag is set...

Page 633: ...ess error detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of P Flash or D Flas...

Page 634: ...he FSTAT register The block erase of a P Flash block is not possible if any of the P Flash sectors contained in the same P Flash block are protected Table 19 13 FERSTAT Field Descriptions Field Descri...

Page 635: ...d unprotected area in P Flash memory as shown inTable 19 16 The FPHS bits can only be written to while the FPHDIS bit is set 2 FPLDIS Flash Protection Lower Address Range Disable The FPLDIS bit determ...

Page 636: ...t can be changed by the user The P Flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is no...

Page 637: ...0 FPLS 1 0 FPHDIS 1 FPLDIS 1 FPHDIS 1 FPLDIS 0 FPHDIS 0 FPLDIS 1 FPHDIS 0 FPLDIS 0 Scenario Scenario Unprotected region Protected region with size Protected region Protected region with size defined...

Page 638: ...to 0 protection enabled If the DPOPEN bit is set the state of the DPS bits is irrelevant During the reset sequence the DFPROT register is loaded with the contents of the D Flash protection byte in th...

Page 639: ...ine the size of the protected area in the D Flash memory as shown in Table 19 20 Table 19 20 D Flash Protection Address Range DPS 4 0 Global Address Range Protected Size 0_0000 0x10_0000 0x10_00FF 256...

Page 640: ...n the FSTAT register all FCCOB parameter fields are locked and cannot be changed by the user until the command completes 1_0110 0x10_0000 0x10_16FF 5888 bytes 1_0111 0x10_0000 0x10_17FF 6144 bytes 1_1...

Page 641: ...ommand code followed by the parameters for this specific Flash command For details on the FCCOB settings required by each command see the Flash command descriptions in Section 19 3 2 19 2 1 12 Flash R...

Page 642: ...ored no other fault information will be recorded until the specific ECC fault flag has been cleared In the event of simultaneous ECC faults the priority for fault recording is double bit fault over si...

Page 643: ...tings ECCRIX 2 0 FECCR Register Content Bits 15 8 Bit 7 Bits 6 0 000 Parity bits read from Flash block 0 Global address 22 16 001 Global address 15 0 010 Data 0 15 0 011 Data 1 15 0 P Flash only 100 D...

Page 644: ...ster read 0 and are not writable 19 2 1 17 Flash Reserved3 Register FRSV3 This Flash register is reserved for factory testing All bits in the FRSV3 register read 0 and are not writable 19 2 1 18 Flash...

Page 645: ...after a reset the user is required to write the FCLKDIV register to divide OSCCLK down to a target FCLK of 1 MHz Table 19 4 shows recommended values for the FDIV field based on OSCCLK frequency NOTE...

Page 646: ...d CAUTION Writes to any Flash register must be avoided while a Flash command is active CCIF 0 to prevent corruption of Flash register contents and Memory Controller behavior 19 3 1 2 1 Define FCCOB Co...

Page 647: ...lation Read FSTAT register Read FSTAT register no START yes Check CCIF Set FCCOB ACCERR FPVIOL Set EXIT Write FCLKDIV register Read FCLKDIV register yes no Clock Register Written Check FDIVLD Set no B...

Page 648: ...SS3 3 Unsecured Special Single Chip mode ST4 4 Unsecured Special Mode NS5 5 Secured Normal Single Chip mode NX6 6 Secured Normal Expanded mode SS7 7 Secured Special Single Chip mode ST8 8 Secured Spec...

Page 649: ...Erase a P Flash or D Flash block An erase of the full P Flash block is only possible when FPLDIS FPHDIS and FPOPEN bits in the FPROT register are set prior to launching the command 0x0A Erase P Flash...

Page 650: ...l 0 If the ACCERR or FPVIOL bits are set in the FSTAT register the user must clear these bits before starting any command write sequence see Section 19 2 1 7 CAUTION A Flash word or phrase must be in...

Page 651: ...in the P Flash memory is erased The Erase Verify P Flash Section command defines the starting point of the code to be verified and the number of phrases The section to be verified cannot cross a Kbyt...

Page 652: ...ion has completed Valid Table 19 32 Erase Verify P Flash Section Command FCCOB Requirements CCOBIX 2 0 FCCOB Parameters 000 0x03 Global address 22 16 of a P Flash block 001 Global address 15 0 of the...

Page 653: ...ess and will then proceed to verify the data words read back as expected The CCIF flag will set after the Program P Flash operation has completed Table 19 35 Read Once Command Error Handling Register...

Page 654: ...d by the Program Once command cannot be erased and any attempt to program one of these phrases a second time will not be allowed Valid phrase index values for the Program Once command range from 0x000...

Page 655: ...mmand launch Set if command not available in current mode see Table 19 25 Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed1 1 If a Program Once phrase...

Page 656: ...to identify Flash block 001 Global address 15 0 in Flash block to be erased Table 19 43 Erase Flash Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 001 a...

Page 657: ...ses security if user supplied keys match those stored in the Flash security bytes of the Flash configuration field see Table 19 45 Erase P Flash Sector Command Error Handling Register Error Bit Error...

Page 658: ...d are aborted set ACCERR until a reset occurs The CCIF flag is set after the Verify Backdoor Access Key operation has completed 19 3 2 12 Set User Margin Level Command The Set User Margin Level comman...

Page 659: ...ses the Memory Controller to set the margin level specified for future read operations of a specific P Flash or D Flash block Table 19 51 Valid Set User Margin Level Settings CCOB CCOBIX 001 Level Des...

Page 660: ...2 14 Erase Verify D Flash Section Command The Erase Verify D Flash Section command will verify that a section of code in the D Flash is erased The Erase Verify D Flash Section command defines the star...

Page 661: ...obal address 22 16 to identify the D Flash block 001 Global address 15 0 of the first word to be verified 010 Number of words to be verified Table 19 57 Erase Verify D Flash Section Command Error Hand...

Page 662: ...le 19 59 Program D Flash Command Error Handling Register Error Bit Error Condition FSTAT ACCERR Set if CCOBIX 2 0 010 at command launch Set if CCOBIX 2 0 101 at command launch Set if command not avail...

Page 663: ...us Register FSTAT and Section 19 2 1 8 Flash Error Status Register FERSTAT The logic used for generating the Flash module interrupts is shown in Figure 19 24 Table 19 61 Erase D Flash Sector Command E...

Page 664: ...Flash configuration field This assumes that you are starting from a mode where the necessary P Flash erase and program commands are available and that the upper region of the P Flash is unprotected I...

Page 665: ...ash security byte can be reprogrammed to the unsecure state if desired In the unsecure state the user has full control of the contents of the backdoor keys by programming addresses 0x7F_FF00 0x7F_FF07...

Page 666: ...Flash module reverts to built in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence If a double bit fault is...

Page 667: ...enter aligned PWM Output slew rate control This module is suited for but not limited to driving small stepper and air core motors used in instrumentation applications This module can be used for other...

Page 668: ...PWM channels are combined and two PWM channels drive four pins 20 1 2 2 2 Full H Bridge Mode This mode is suitable to drive any load requiring a PWM signal in a H bridge configuration using two pins...

Page 669: ...ator M0C0M M0C0P Duty Register 1 Comparator M0C1M M0C1P Duty Register 2 Comparator M1C0M M1C0P Duty Register 3 Comparator M1C1M M1C1P Duty Register 4 Comparator M2C0M M2C0P Duty Register 5 Comparator...

Page 670: ...motor drive These pins interface to the coils of motor 1 PWM output on M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state PWM output on M1C1M results in...

Page 671: ...1 Module Memory Map Figure 20 2 shows the memory map of the 10 bit 8 channel motor controller module Figure 20 2 MC10B8C Memory Map Offset Register Access 0x0000 Motor Controller Control Register 0 MC...

Page 672: ...cle Register 3 MCDC3 High Byte RW 0x0027 Motor Controller Duty Cycle Register 3 MCDC3 Low Byte RW 0x0028 Motor Controller Duty Cycle Register 4 MCDC4 High Byte RW 0x0029 Motor Controller Duty Cycle Re...

Page 673: ...tions of MCPRE1 and MCPRE0 4 MCSWAI Motor Controller Module Stop in Wait Mode 0 Entering wait mode has no effect on the motor controller module and the associated port pins maintain the functionality...

Page 674: ...outputs in dual full H bridge modes In half H bridge mode the PWM output is always active low RECIRC 1 will also invert the effect of the S bits refer to Section 20 4 1 3 2 Sign Bit S in dual full H...

Page 675: ...ol registers after the next period timer counter overflow In this case the motor controller releases all pins NOTE Programming MCPER to 0x0001 and setting the DITH bit will be managed as if MCPER is p...

Page 676: ...l the PWM channel s PWM alignment mode and operation See Table 20 8 MCAM 1 0 and MCOM 1 0 are double buffered The values used for the generation of the output waveform will be copied to the working re...

Page 677: ...ber of motor controller timer counter clocks the corresponding output is driven low RECIRC 0 or is driven high RECIRC 1 Setting all bits to 0 will give a static high output in case of RECIRC 0 otherwi...

Page 678: ...idge mode A PWM channel pair is configured to work in Dual Full H Bridge mode and a PWM timer counter overflow occurs after the odd6 duty cycle register of the channel pair has been written In this wa...

Page 679: ...bridge mode or will be released while in half H bridge mode The state of the S bit in the duty cycle register determines the pin where the PWM signal is driven in full H bridge mode While in half H br...

Page 680: ...will be an output high or low This results in motor recirculation currents on the high side drivers RECIRC 0 while the PWM signal is at a logic high level or motor recirculation currents on the low si...

Page 681: ...rites to the duty cycle register x will result in the previous data being overwritten 20 4 1 1 2 Full H Bridge Mode MCOM 10 In full H bridge mode the PWM channels x and x 1 operate independently The d...

Page 682: ...in full H bridge mode the other as programmed 20 4 1 3 Relationship Between Sign Duty Dither RECIRC Period and PWM Mode Functions 20 4 1 3 1 PWM Alignment Modes Each PWM channel can be programmed ind...

Page 683: ...er aligned mode might start with the odd period if the channel has not been disabled before changing the alignment mode to center aligned 0 15 PWM Output 0 1 Period 100 Counts Motor Controller Timer C...

Page 684: ...case the active state of the PWM signal will be high See Table 20 12 for detailed information about the impact of SIGN and RECIRC bit on the PWM output 20 4 1 3 3 RECIRC Bit The RECIRC bit controls th...

Page 685: ...ged only while no PWM channel is operated in dual full H bridge mode Figure 20 12 PWM Active Phase RECIRC 0 S 0 Figure 20 13 PWM Passive Phase RECIRC 0 S 0 VDDM VSSM MnC0P MnC0M Static 0 PWM 1 PWM 1 S...

Page 686: ...reescale Semiconductor Figure 20 14 PWM Active Phase RECIRC 1 S 0 Figure 20 15 PWM Passive Phase RECIRC 1 S 0 VSSM MnC0P MnC0M VDDM Static 1 Static 1 PWM 0 PWM 0 VDDM VSSM MnC0P MnC0M Static 1 Static...

Page 687: ...Modes Mode MCOM 1 0 PWM Duty RECIRC S T1 T2 T3 T4 Off Don t care Don t care Don t care Half H Bridge 00 Active Don t care Don t care OFF ON Half H Bridge 00 Passive Don t care Don t care ON OFF Half H...

Page 688: ...tput compare between motor controller timer counter and DUTY occurs the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter over...

Page 689: ...by P 10 1 1 in MCPER After the motor controller timer counter resets to 0x000 the PWM output will return to a logic low level This process will repeat every number of counts of the motor controller ti...

Page 690: ...DC 31 MCPER 200 RECIRC 0 PWM Output 1 Period 100 Counts Motor Controller Timer Counter Motor Controller Timer Counter Clock 100 Counts 0 15 16 0 0 16 15 99 99 0 84 PWM Output 85 0 1 Period 100 Counts...

Page 691: ...source is selected Figure 20 22 Motor Controller Counter Clock Selection The peripheral bus clock is the source for the motor controller counter prescaler The motor controller counter clock rate fTC i...

Page 692: ...t large peak current draw from the motor power supply selectable delays can be used to stagger the high logic level to low logic level transitions on the motor controller outputs The timing delay td i...

Page 693: ...ule clocks are stopped and the associated port pins are set to their inactive state which is defined by the state of the RECIRC bit The motor controller module registers stay the same as they were pri...

Page 694: ...0 11 ii Left aligned PWM MCAM 1 0 01 iii No channel delay MCCD 1 0 00 2 Perform the startup phase a Clear the duty cycle registers MCDC0 and MCDC1 b Initialize the period register MCPER which is equi...

Page 695: ...MCDC2_HI EQU MC_START 24 MCDC2_LO EQU MC_START 25 MCDC3_HI EQU MC_START 26 MCDC3_LO EQU MC_START 27 Port defines DDRB EQU 0003 PORTB EQU 0001 Flash defines FLASH_START EQU 0100 FCMD EQU FLASH_START 0...

Page 696: ...TIM_SR yes go to TIM_SR BRA MAIN TIM_SR LDX TEMP_X restore index register X LDAA PORTB if PB 0 enter shutdown routine ANDA 01 BNE SHUTDOWN LDX TEMP_X restore index register X BEQ NEW_SEQ all mc config...

Page 697: ...T DC B 02 FF7 MCDC1_HI MCDC1_LO DC B 02 D0 MCDC0_HI MCDC0_LO DC B 02 A0 MCDC1_HI MCDC1_LO DC B 02 90 MCDC0_HI MCDC0_LO DC B 02 60 MCDC1_HI MCDC1_LO DC B 02 25 MCDC0_HI MCDC0_LO 7 The values for the du...

Page 698: ...Motor Controller MC10B8CV1 MC9S12XHY Family Reference Manual Rev 1 01 698 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 699: ...tor the blanking time and the integration time The value in the accumulator represents the change in linked flux magnetic flux times the number of turns in the coil and can be compared to a stored thr...

Page 700: ...VDDM COSxP COSxM T1 T2 T3 VSSM 1 2 1 2 1 2 1 8 4 1 MUX VDDM T4 VSSM S1 S3 S2 S4 VDDM SINxP SINxM T5 T6 T7 VSSM VDDM T8 VSSM S5 S7 S6 S8 16 bit accumulator register VDDM VSSM R2 R2 DFF 16 bit modulus d...

Page 701: ...and stepper motor B if two motors are connected 21 2 1 COSxM COSxP Cosine Coil Pins for Motor x These pins interface to the cosine coils of a stepper motor to measure the back EMF for calibration of t...

Page 702: ...is determined at the MCU level and is given in the Device Overview chapter The address offset is defined at the block level and is given here 21 3 2 Register Descriptions This section describes in det...

Page 703: ...a reset state and the accumulator is initialized to zero Table 21 5 shows the condition state of each switch from Figure 21 1 based on the ITG STEP and POL bits 0 Blanking 1 Integration 6 DCOIL Drive...

Page 704: ...ration mode Table 21 4 Transistor Condition States RTZE 1 STEP ITG DCOIL RCIR T1 T2 T3 T4 T5 T6 T7 T8 xx 1 0 x OFF OFF OFF OFF OFF OFF OFF OFF 00 0 0 0 OFF OFF OFF OFF ON OFF ON OFF 00 0 0 1 OFF OFF O...

Page 705: ...11 0 Close Open Open Close Open Open Open Open 1 11 1 Open Close Close Open Open Open Open Open Table 21 6 Full Step States STEP Pole Angle COSINE Coil Current SINE Coil Current Coil Node to Integrato...

Page 706: ...eturn the contents of the load register 4 PRE Prescaler 0 The modulus down counter clock frequency is the bus frequency divided by 64 1 The modulus down counter clock frequency is the bus frequency di...

Page 707: ...s on off control over the SSD allowing reduced MCU power consumption Because the analog circuit is turned off when powered down the sigma delta converter requires a recovery time after exit from Wait...

Page 708: ...eaches 0x0000 If not masked MCZIE 1 a modulus counter underflow interrupt is pending while this flag is set This flag is cleared by writing a 1 to the bit A write of 0 has no effect 0 AOVIF Accumulato...

Page 709: ...ount down from this value and will stop at 0x0000 If modulus mode is enabled MODMC 1 a write to the MDCCNT register updates the load register with the value written to it The count register will not b...

Page 710: ...signed register The SSD also has a 16 bit modulus down counter to monitor blanking and integration times DC offset compensation is implemented when using the modulus down counter to monitor integratio...

Page 711: ...rectify and integrate the back EMF produced by the coils to detect stepped rotary motion DC offset compensation is implemented when using the modulus down counter to monitor integration time 21 4 2 Fu...

Page 712: ...he SINx and COSx H bridges when STEP 1 DCOIL 1 ITG 0 and RCIR 1 Figure 21 12 Current Flow when STEP 1 DCOIL 1 ITG 0 RCIR 1 Figure 21 13 shows the current flow in the SINx and COSx H bridges when STEP...

Page 713: ...OIL 1 ITG 1 Figure 21 14 shows the current flow in the SINx and COSx H bridges when STEP 3 DCOIL 1 and ITG 1 Figure 21 14 Current flow when STEP 3 DCOIL 1 ITG 1 VDDM COSxP COSxM T1 T2 T3 T4 VSSM VDDM...

Page 714: ...time the integration result should be ignored Wait mode with SSDWAI bit set powers down the sigma delta converter and halts the clock to the modulus counter Exit from Wait enables the sigma delta con...

Page 715: ...or set POL clear or set SMS 2 Set MCZIE clear MODMC clear or set PRE set MCEN 3 Set RTZE set SDCPU write ACLKS select sample frequency 4 Store threshold value in RAM 1 Clear MCZIF 2 Write MDCCNT with...

Page 716: ...Stepper Stall Detector SSDV1 Block Description MC9S12XHY Family Reference Manual Rev 1 01 716 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 717: ...e following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification is shown in the column labeled C in the parameter tables where app...

Page 718: ...and VDDX VSS35 is used for either VSSA and VSSX unless otherwise noted IDD35 denotes the sum of the currents flowing into the VDDA and VDDR pins The Run mode current in the VDDX domain is external lo...

Page 719: ...st risk when the MCU is not consuming power e g if no system clock is present or if clock rate is very low which would reduce overall power consumption A 1 5 Absolute Maximum Ratings Absolute maximum...

Page 720: ...upply voltage2 2 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The absolute maximum ratings apply when the device is powered from an exte...

Page 721: ...ance C 100 pF Number of pulse per pin Positive Negative 1 1 Charged Device Number of pulse per pin Positive Negative 3 3 Latch up Minimum input voltage limit 2 5 V Maximum input voltage limit 7 5 V Ta...

Page 722: ...MHz Temperature Option C Operating junction temperature range Operating ambient temperature range5 TJ TA 40 40 27 85 C Temperature Option V Operating junction temperature range Operating ambient tempe...

Page 723: ...internal voltage regulator enabled and disabled must be considered 1 Internal voltage regulator disabled 2 Internal voltage regulator enabled P D P INT P IO P INT Chip Internal Power Dissipation W P...

Page 724: ...per JEDEC JESD51 8 Thermal test board meets JEDEC specification for the specified package JB 37 C W 6 D Junction to Case4 4 Junction to Case at the top of the package determined using MIL STD 883 Meth...

Page 725: ...age current pins in high impedance input mode all except PU PV Vin VDD35 or VSS35 25 C 150 C I in 1 26 nA C Input leakage current pins in high impedance input mode PU PV Vin VDD35 or VSS35 25 C 150 C...

Page 726: ...x RPUL 25 90 K P Internal pull up device current PU PV VIH min input voltage VIL max IPUL 10 130 A 12 P Internal pull down device resistance all except PU PV VIH min input voltage VIL max RPDH 25 90 K...

Page 727: ...the module is enabled and the comparators are configured to trigger in outside range The range covers all the code executed by the core the tracing is disabled CAN0 CAN1 Configured to loop back mode...

Page 728: ...led and the comparators are configured to trigger in outside range The range covers all the code executed by the core the tracing is disabled CAN0 CAN1 Configured to loop back mode using a bit rate of...

Page 729: ...5 9 mA 2 T MSCAN 0 7 3 T SPI 0 3 4 T SCI 0 1 5 T PWM 0 4 6 T IIC 0 2 7 T LCD 0 3 8 T MC 0 4 9 T SSD 0 7 10 T TIM 0 3 11 T ATD 0 7 12 T Overhead 10 7 Conditions are shown in Table A 4 unless otherwise...

Page 730: ...led LCD disabled PLL off LCP mode 11a C C C 40 C 25 C 150 C IDDPS 180 220 500 A Pseudo stop current API RTI and COP enabled LCD disabled PLL off FSP mode 11b C C C 40 C 25 C 150 C IDDPS 460 530 910 A...

Page 731: ...res are implemented to minimize the affect of output driver noise it Conditions are shown in Table A 4 unless otherwise noted supply voltage 3 13 V VDDA 5 5 V Num C Rating Symbol Min Typ Max Unit 1 D...

Page 732: ...an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltag...

Page 733: ...A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 C Max input source resistance1 1 Refer to A 2 2 2 for further information concerning source resistance RS 1 K 2 D Total input capacit...

Page 734: ...For the following definitions see also Figure A 1 Differential non linearity DNL is defined as the difference between two adjacent switching steps The integral non linearity INL is defined as the sum...

Page 735: ...d Table A 15 1 5 Vin mV 10 15 20 25 30 35 40 85 90 95 100 105 110 115 120 65 70 75 80 60 0 3 2 5 4 7 6 45 3F7 3F9 3F8 3FB 3FA 3FD 3FC 3FE 3FF 3F4 3F6 3F5 8 9 1 2 FF FE FD 3F3 10 Bit Resolution 8 Bit R...

Page 736: ...ted in 12 bit mode 2 Better performance is possible using specially designed multi layer PCBs or averaging techniques Symbol Min Typ Max Unit 1 P Resolution 10 Bit LSB 5 mV 2 P Differential Nonlineari...

Page 737: ...t on the location of the first non blank word starting at relative address zero It takes one bus cycle per phrase to verify plus a setup of the command Assuming that no non blank location is found the...

Page 738: ...time can be calculated using the following equation A 3 1 6 P Flash Program Once FCMD 0x07 The maximum P Flash Program Once time is given by A 3 1 7 Erase All Blocks FCMD 0x08 Erasing all blocks takes...

Page 739: ...maximum time for unsecuring the flash is given by A 3 1 11 Verify Backdoor Access Key FCMD 0x0C The maximum verify backdoor access key time is given by A 3 1 12 Set User Margin Level FCMD 0x0D The ma...

Page 740: ...reby Nw denotes the number of words BC 0 if no boundary is crossed and BC 1 if a boundary is crossed The maximum programming time can be calculated using the following equation A 3 1 16 Erase D Flash...

Page 741: ...Hz unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 D External oscillator clock fNVMOSC 2 401 1 Restrictions for oscillator in crystal mode apply MHz 2 D Bus frequency for programming or...

Page 742: ...ase refer to Engineering Bulletin EB618 Years 2 C Data retention at an average junction temperature of TJavg 85 C3 after less than 100 program erase cycles 3 TJavg does not exceed 85 C in a typical te...

Page 743: ...de Indicates I O ADC performance degradation due to low supply voltage VLVIA VLVID 4 04 4 19 4 23 4 38 4 40 4 49 V V 6 P VDDX Low Voltage Reset 2 3 Assert Level Deassert Level 2 Device functionality i...

Page 744: ...Drops LVI low voltage interrupt POR power on reset and LVRs low voltage reset handle chip power up or drops of the supply voltage Their function is shown in Figure A 2 Figure A 2 9S12XHY family Chip...

Page 745: ...amily Power Sequencing During power sequencing VDDA can be powered up before VDDR VDDX VDDR and VDDX must be powered up together adhering to the operating conditions differential VRH power up must fol...

Page 746: ...out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG flags register has not been set A 6 1 3 External Reset When external reset is asserted...

Page 747: ...p and Wait Recovery The recovery from pseudo stop and wait is essentially the same since the oscillator is not stopped in both modes The controller can be woken up by internal or external interrupts A...

Page 748: ...tal resonator requirements tUPOSC 2 2 10 ms 3b C Oscillator start up time LCP 8MHz 1 tUPOSC 1 1 8 ms 3c C Oscillator start up time LCP 16MHz 1 tUPOSC 0 75 5 ms 5 D Clock Quality check time out tCQOUT...

Page 749: ...ns The relative deviation of tnom is at its maximum for one clock period and decreases towards zero for larger number of clock periods N Defining the jitter as For N 1000 the following equation is a g...

Page 750: ...ion from target frequency 5 D Un Lock Detection unl 0 5 2 5 2 7 C Time to lock tlock 214 150 256 fREF s 8 C Jitter fit parameter 13 3 fOSC 4MHz fBUS 40MHz equivalent fPLL 80MHz REFDIV 00 REFRQ 01 SYND...

Page 751: ...VLCD After a positive spike on VBuf a frontplane or backplane is discharged by an active load with a constant current After a negative spike on VBuf the output is charged through a transistor which is...

Page 752: ...nductor Figure A 7 VBuf transients not to scale Figure A 8 buffer output characteristic VBuf t 2 3VLCD 1 2VLCD 1 3VLCD constant current resistive IOUT VOUT 1 3 1 2 or 2 3 VLCD resistive current source...

Page 753: ...CAN Table A 24 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P MSCAN wakeup dominant pulse filtered tWUP 1 5 s 2 P...

Page 754: ...nditions Description Value Unit Drive mode Full drive mode Load capacitance CLOAD 1 on all outputs 1 Timing specified for equal load on all SPI output pins Avoid asymmetric load 50 pF Thresholds for d...

Page 755: ...from 16MHZ and fbus 2MHZ same for the other MIN X Y 5 MAX 62 5 2 tbus means select the maximum period value from 62 5ns and 2 tbus ns same for the other MAX X Y 1 D SCK period tsck MAX 62 5 2 tbus 1...

Page 756: ...t CPHA 1 is depicted Figure A 12 SPI Slave Timing CPHA 1 SCK Input SCK Input MOSI Input MISO Output SS Input 1 9 5 6 MSB IN Bit MSB 1 1 LSB IN Slave MSB Slave LSB OUT Bit MSB 1 1 11 4 4 2 7 CPOL 0 CPO...

Page 757: ...rate control should be enabled 1 D SCK period tsck 4 tbus 1 ns MAX 1250 4 tbus 2 2 D Enable lead time tlead 4 tbus 3 D Enable lag time tlag 4 tbus 4 D Clock SCK high or low time twsc k 4 tbus 5 D Dat...

Page 758: ...Reference Manual Rev 1 01 758 Freescale Semiconductor Appendix B Package and Die Information This section provides the physical dimensions of the 9S12XHY family packages information Downloaded from E...

Page 759: ...mation MC9S12XHY Family Reference Manual Rev 1 01 Freescale Semiconductor 759 B 1 112 pin LQFP Mechanical Dimensions Figure B 1 112 pin LQFP case no 987 page 1 Downloaded from Elcodis com electronic c...

Page 760: ...ckage and Die Information MC9S12XHY Family Reference Manual Rev 1 01 760 Freescale Semiconductor Figure B 2 112 pin LQFP case no 987 page 2 Downloaded from Elcodis com electronic components distributo...

Page 761: ...ckage and Die Information MC9S12XHY Family Reference Manual Rev 1 01 Freescale Semiconductor 761 Figure B 3 112 pin LQFP case no 987 page 3 Downloaded from Elcodis com electronic components distributo...

Page 762: ...mation MC9S12XHY Family Reference Manual Rev 1 01 762 Freescale Semiconductor B 2 100 Pin LQFP Mechanical Dimensions Figure B 4 100 pin LQFP case no 983 page 1 Downloaded from Elcodis com electronic c...

Page 763: ...ckage and Die Information MC9S12XHY Family Reference Manual Rev 1 01 Freescale Semiconductor 763 Figure B 5 100 pin LQFP case no 983 page 2 Downloaded from Elcodis com electronic components distributo...

Page 764: ...ckage and Die Information MC9S12XHY Family Reference Manual Rev 1 01 764 Freescale Semiconductor Figure B 6 100 pin LQFP case no 983 page 3 Downloaded from Elcodis com electronic components distributo...

Page 765: ...ot place other signals or supplies underneath area occupied by C12 C11 and Q1 and the connection area to the MCU Central power input should be fed in at the VDDA VSSA pins Example layouts are illustra...

Page 766: ...Reference Manual Rev 1 01 766 Freescale Semiconductor C 1 1 112 Pin LQFP Recommended PCB Layout Figure C 1 112 Pin LQFP Recommended PCB Layout Loop Controlled Pierce Oscillator Downloaded from Elcodis...

Page 767: ...Reference Manual Rev 1 01 Freescale Semiconductor 767 C 1 2 100 Pin QFP Recommended PCB Layout Figure C 2 100 Pin QFP Recommended PCB Layout Loop Controlled Pierce Oscillator Downloaded from Elcodis...

Page 768: ...ata Flash 9S12XHY256 112 LQFP 256K 12K 8K 100 QFP 9S12XHY128 112 LQFP 128K 8K 8K 100 QFP Table D 2 Peripheral Options of 9S12XHY family Members Device Package CAN SCI SPI TIM IIC LCD MC A D PWM 9S12XH...

Page 769: ...ort Integration Module PIM Map 2 of 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x000C PUCR R 0 BKPUR 0 0 0 0 PUPBE PUPAE W 0x000D Reserved R 0 0 0 0 0 0 0 0 W 0x000E 0x000F Reserve...

Page 770: ...8 Reserved R 0 0 0 0 0 0 0 0 W 0x0019 Reserved R 0 0 0 0 0 0 0 0 W 0x001A 0x001B Device ID register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x001A PARTIDH R PARTIDH W 0x001B PARTI...

Page 771: ...0 0 SC3 SC2 SC1 SC0 W 0x0027 DBGMFR R 0 0 0 0 MC3 MC2 MC1 MC0 W 0x00281 1 This represents the contents if the Comparator A or C control register is blended into this address DBGXCTL COMPA C R 0 NDB T...

Page 772: ...5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0034 SYNR R VCOFRQ 1 0 SYNDIV 5 0 W 0x0035 REFDV R REFFRQ 1 0 REFDIV 5 0 W 0x0036 POSTDIV R 0 0 0 POSTDIV 4 0 W 0x0037 CRGFLG R RTIF PORF LVRF LOCKIF LOCK ILAF SCMIF...

Page 773: ...TL1 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W 0x0049 TCTL2 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W 0x004A TCTL3 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A W 0x004B TCTL4 R EDG3B EDG3A EDG2B EDG2A EDG1B E...

Page 774: ...Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x005E TC7H R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x005F TC7L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0060 PACTL R 0 PAEN PAMOD PEDGE...

Page 775: ...0x007C ATDDIENH R 0 0 0 0 IEN 11 8 W 0x007D ATDDIENL R IEN 7 0 W 0x007E ATDCMPHTH R 0 0 0 0 CMPHT 11 8 W 0x007F ATDCMPHTL R CMPHT 7 0 W 0x0080 ATDDR0 R See Section 10 3 2 12 1 Left Justified Result Da...

Page 776: ...Right Justified Result Data DJM 1 W 0x0096 ATDDR11 R See Section 10 3 2 12 1 Left Justified Result Data DJM 0 and Section 10 3 2 12 2 Right Justified Result Data DJM 1 W 0x0098 0x009F Unimple mented...

Page 777: ...2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x00B2 PWMCNT6 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x00B3 PWMCNT7 R Bit 7 6 5 4 3 2 1 Bit 0 W 0 0 0 0 0 0 0 0 0x00B4 PWMPER0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x00B5 PWMP...

Page 778: ...00C7 Reserved R 0 0 0 0 0 0 0 0 W 0x00C8 0x00CF Asynchronous Serial Interface SCI0 Map Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x00C8 SCI0BDH1 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 S...

Page 779: ...SCI1CR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x00D0 SCI1ASR12 2 Those registers are accessible if the AMAP bit in the SCI1SR2 register is set to one R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W 0x00D1 S...

Page 780: ...Bit 0 0x00E0 IBAD R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 W 0x00E1 IBFD R IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 W 0x00E2 IBCR R IBEN IBIE MS SL TX RX TXAK 0 0 IBSWAI W RSTA 0x00E3 IBSR R TCF IAAS IB...

Page 781: ...MGBUSY RSVD MGSTAT1 MGSTAT0 W 0x0107 FERSTAT R 0 0 0 0 0 0 DFDIF SFDIF W 0x0108 FPROT R FPOPEN RNV6 FPHDIS FPHS1 FPHS0 FPLDIS FPLS1 FPLS0 W 0x0109 DFPROT R DPOPEN 0 0 DPS4 DPS3 DPS2 DPS1 DPS0 W 0x010...

Page 782: ...0 W 0x0123 Reserved R 0 0 0 0 0 0 0 0 W 0x0124 Reserved R 0 0 0 0 0 0 0 0 W 0x0125 Reserved R 0 0 0 0 0 0 0 0 W 0x0126 INT_XGPRIO R 0 0 0 0 0 XILVL 2 0 W 0x0127 INT_CFADDR R INT_CFADDR 7 4 0 0 0 0 W 0...

Page 783: ...145 CAN0RIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0146 CAN0TFLG R 0 0 0 0 0 TXE2 TXE1 TXE0 W 0x0147 CAN0TIER R 0 0 0 0 0 TXEIE2 TXEIE1 TXEIE0 W 0x0148 CAN0TARQ R 0 0 0 0 0 ABT...

Page 784: ...ID0 RTR IDE 0 CANxRIDR1 W 0xXXX2 Extended ID R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 Standard ID R CANxRIDR2 W 0xXXX3 Extended ID R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR Standard ID R CANxRIDR3 W 0xXXX4 0xXX...

Page 785: ...R CANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK W 0x0182 CAN1BTR0 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 W 0x0183 CAN1BTR1 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 W 0x0184 CAN1RFL...

Page 786: ...d MSCAN Foreground Receive and Transmit Buffer Layout W 0x01B0 0x01BF CAN1TXFG R FOREGROUND TRANSMIT BUFFER See Detailed MSCAN Foreground Receive and Transmit Buffer Layout W Address Name Bit 7 Bit 6...

Page 787: ...6 D5 D4 D3 D2 D1 D0 W 0x01E4 MCDC2 hi R S S S S S D10 D9 D8 W 0x01E5 MCDC2 lo R D7 D6 D5 D4 D3 D2 D1 D0 W 0x01E6 MCDC3 hi R S S S S S D10 D9 D8 W 0x01E7 MCDC3 lo R D7 D6 D5 D4 D3 D2 D1 D0 W 0x01E8 MCD...

Page 788: ...P35EN FP34EN FP33EN FP32EN W 0x0207 Reserved R 0 0 0 0 0 0 0 0 W 0x0208 LCDRAM0 R FP1BP3 FP1BP2 FP1BP1 FP1BP0 FP0BP3 FP0BP2 FP0BP1 FP0BP0 W 0x0209 LCDRAM1 R FP3BP3 FP3BP2 FP3BP1 FP3BP0 FP2BP3 FP2BP2 F...

Page 789: ...2 FP30BP1 FP30BP0 W 0x0218 LCDRAM16 R FP33BP3 FP33BP2 FP33BP1 FP33BP0 FP32BP3 FP32BP2 FP32BP1 FP32BP0 W 0x0219 LCDRAM17 R FP35BP3 FP35BP2 FP35BP1 FP35BP0 FP34BP3 FP34BP2 FP34BP1 FP34BP0 W 0x021A LCDRA...

Page 790: ...1FLG R MCZIF 0 0 0 0 0 0 AOVIF W 0x022C MDC1CNTH R MDCCNT 15 8 W 0x022D MDC1CNTL R MDCCNT 7 0 W 0x022E ITG1ACCH R ITGACC 15 8 W 0x022F ITG1ACCL R ITGACC 7 0 W 0x0230 0x0237 Stepper Stall Detector 2 SS...

Page 791: ...3CNTL R MDCCNT 7 0 W 0x023E ITG3ACCH R ITGACC 15 8 W 0x023F ITG3ACCL R ITGACC 7 0 W 0x0240 0x029F Port Integration Module PIM Map 4 of 4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x...

Page 792: ...M3 PTIM2 PTIM1 PTIM0 W 0x0252 DDRM R 0 0 0 0 DDRM3 DDRM2 DDRM1 DDRM0 W 0x0253 Reserved R 0 0 0 0 0 0 0 0 W 0x0254 PERM R 0 0 0 0 PERM3 PERM2 PERM1 PERM0 W 0x0255 PPSM R 0 0 0 0 PPSM3 PPSM2 PPSM1 PPSM0...

Page 793: ...PT1AD 2 PT1AD 1 PT1AD 0 W 0x0272 DDR0AD R 0 0 0 0 DDR0AD 3 DDR0AD 2 DDR0AD 1 DDR0AD 0 W 0x0273 DDR1AD R DDR1AD 7 DDR1AD 6 DDR1AD 5 DDR1AD 4 DDR1AD 3 DDR1AD 2 DDR1AD 1 DDR1AD 0 W 0x0274 Reserved R 0 0...

Page 794: ...W 0x028F PIFR R 0 0 0 PIFR4 PIFR3 PIFR2 PIFR1 PIFR0 W 0x0290 PTU R PTU7 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0 W 0x0291 PTIU R PTIU7 PTIU6 PTIU5 PTIU4 PTIU3 PTIU2 PTIU1 PTIU0 W 0x0292 DDRU R DDRU7 DDRU6 D...

Page 795: ...D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 W 0x02A4 TCNTH R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W 0x02A5 TCNTL R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W 0x02A6 TSCR1 R TEN TSWAI TSFR...

Page 796: ...TC4L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x02BA TC5H R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x02BB TC5L R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x02BC TC...

Page 797: ...x02F1 VREGCTRL R 0 0 0 0 0 LVDS LVIE LVIF W 0x02F2 VREGAPICL R APICLK 0 0 APIFES APIEA APIFE APIE APIF W 0x02F3 VREGAPITR R APITR5 APITR4 APITR3 APITR2 APITR1 APITR0 0 0 W 0x02F4 VREGAPIRH R APIR15 AP...

Page 798: ...y Reference Manual Rev 1 01 798 Freescale Semiconductor 0x0400 0x07FF Reserved Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x0400 0x07FF Reserved R 0 0 0 0 0 0 0 0 W Downloaded from E...

Page 799: ...number NOTE The mask identifier suffix and the Tape Reel suffix are always both omitted from the part number which is actually marked on the device For specific part numbers to order please contact y...

Page 800: ...Ordering Information MC9S12XHY Family Reference Manual Rev 1 01 800 Freescale Semiconductor Downloaded from Elcodis com electronic components distributor...

Page 801: ...Downloaded from Elcodis com electronic components distributor...

Page 802: ...ed in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be...

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