Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
124
Freescale Semiconductor
2.3.58
Port AD Data Direction Register (DDR0AD)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT1AD registers, when changing the
DDR1AD register.
Table 2-47. PT1AD Register Field Descriptions
Field
Description
7-0
PT1AD
Port AD general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Address 0x0272
Access: User read/write
1
1
Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
0
0
0
0
DDR0AD3
DDR0AD2
DDR0AD1
DDR0AD0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-55. Port AD Data Direction Register (DDR1AD)
Table 2-48. DDR0AD Register Field Descriptions
Field
Description
3-0
DDR0AD
Port AD data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”.
1 Associated pin is configured as output
0 Associated pin is configured as input
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