Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
125
2.3.59
Port AD Data Direction Register (DDR1AD)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT1AD registers, when changing the
DDR1AD register.
2.3.60
PIM Reserved Register
Address 0x0273
Access: User read/write
1
1
Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
DDR1AD7
DDR1AD6
DDR1AD5
DDR1AD4
DDR1AD3
DDR1AD2
DDR1AD1
DDR1AD0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-56. Port AD Data Direction Register (DDR1AD)
Table 2-49. DDR1AD Register Field Descriptions
Field
Description
7-0
DDR1AD
Port AD data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”.
1 Associated pin is configured as output
0 Associated pin is configured as input
Address 0x0274
Access: User read
1
1
Read: Always reads 0x00
Write: Unimplemented
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-57. PIM Reserved Register
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