Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
131
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
2.3.68
PIM Reserved Registers
2.3.69
Port R Pull Device Enable Register (PERR)
1
DDRR
Port R data direction—
This register controls the data direction of pin 1.This register configures pin as either input or output.
If TIM0 are routing to the PR and TIM0 output compare functions are enabled, it will force as output.
Else If TX of CAN1 is routing to PR and CA1 is enabled, it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0
DDRR
Port R data direction—
This register controls the data direction of pin 3-0.This register configures pin as either input or output.
If TIM1/TIM0 are routing to the PR and TIM1/TIM0 output compare functions are enabled, it will force as output.
Else If RX of CAN1 is routing to PR and CA1 is enabled, it will force as input.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Address 0x0283
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-65. PIM Reserved Register
Address 0x0284
Access: User read/write
1
7
6
5
4
3
2
1
0
R
PERR7
PERR6
PERR5
PERR4
PERR3
PERR2
PERR1
PERR0
W
Reset
1
1
1
1
1
1
1
1
Figure 2-66. Port R Pull Device Enable Register (PERR)
Table 2-54. DDRR Register Field Descriptions (continued)
Field
Description
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