Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
135
2.3.76
Port S Interrupt Flag Register (PIFS)
2.3.77
Port AD Interrupt Enable Register (PIE1AD)
Read: Anytime.
Address 0x028B
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
0
PIFS6
PIFS5
0
PIFS3
PIFS2
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-73. Port S Interrupt Flag Register (PIFS)
Table 2-61. PIFS Register Field Descriptions
Field
Description
6-5 3-2
PIFS
Port S interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSS register. To clear this flag, write logic level 1 to the corresponding bit in the PIFS register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
Address 0x028C
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
PIE1AD7
PIE1AD6
PIE1AD5
PIE1AD4
PIE1AD3
PIE1AD2
PIE1AD1
PIE1AD0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-74. Port AD Interrupt Enable Register (PIE1AD)
Table 2-62. PIE1AD Register Field Descriptions
Field
Description
7-0
PIE1AD
Port AD interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port AD.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
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