Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
137
2.3.80
Port R Interrupt Flag Register (PIFR)
2.3.81
Port U Data Register (PTU)
Address 0x028F
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
0
0
0
PIFR4
PIFR3
PIFR2
PIFR1
PIFR0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-77. Port R Interrupt Flag Register (PIFR)
Table 2-65. PIFR Register Field Descriptions
Field
Description
4-0
PIFR
Port R interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSR register. To clear this flag, write logic level 1 to the corresponding bit in the PIFR register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
Address 0x0290
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
PTU7
PTU6
PTU5
PTU4
PTU3
PTU2
PTU1
PTU0
W
—
IOC0_3
—
IOC0_2
—
IOC0_1
—
IOC0_0
Altern.
Function
M1C1P
M1C1M
M1C0P
M1C0M
M0C1P
M0C1M
M0C0P
M0C0M
M1SINP
M1SINM
M1COSP
M1COSM
M0SINP
M0SINM
M0COSP
M0COSM
Reset
0
0
0
0
0
0
0
0
Figure 2-78. Port U Data Register (PTU)
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