Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
151
2.4.2.1
Data register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration (
Figure 2-94
).
2.4.2.2
Input register (PTIx)
This register is read-only and always returns the buffered state of the pin (
Figure 2-94
).
2.4.2.3
Data direction register (DDRx)
This register defines whether the pin is used as an general purpose input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (
Figure 2-94
).
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (
2.4.2.1/2-151
).
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on port data or port input registers, when
changing the data direction register.
Table 2-80. Register availability per port
1
1
Each cell represents one register with individual configuration bits
Port
Data
Input
Data
Direction
Reduced
Drive
Pull
Enable
Polarity
Select
Wired-
Or Mode
Slew
Rate
Interrupt
Enable
Interrupt
Flag
Routing
A
yes
-
yes
no
yes
-
-
-
-
-
-
B
yes
-
yes
-
-
-
-
-
-
T
yes
yes
yes
no
yes
yes
-
-
yes
yes
yes
S
yes
yes
yes
no
yes
yes
yes
-
yes
yes
yes
M
yes
yes
yes
no
yes
yes
yes
-
no
no
no
R
yes
yes
yes
no
yes
yes
yes
-
yes
yes
no
P
yes
yes
yes
no
yes
yes
-
-
-
-
yes
H
yes
yes
yes
no
yes
yes
yes
-
-
-
yes
AD
yes
-
yes
no
yes
-
-
-
yes
yes
-
U
yes
yes
yes
no
yes
yes
-
yes
-
-
yes
V
yes
yes
yes
no
yes
yes
-
yes
-
-
yes
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