Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
155
Table 2-81. Pulse Detection Criteria
Figure 2-96. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE=1) and interrupt flag not set (PIF=0).
2.5
Initialization Information
2.5.1
Port Data and Data Direction Register writes
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins
from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data
register before enabling the outputs.
Pulse
Mode
STOP
STOP
1
1
These values include the spread of the oscillator frequency over tempera-
ture, voltage and process.
Unit
Ignored
t
pulse
≤
3
bus clocks
t
pulse
≤
t
pign
Uncertain
3 < t
pulse
< 4
bus clocks
t
pign
< t
pulse
< t
pval
Valid
t
pulse
≥
4
bus clocks
t
pulse
≥
t
pval
t
pulse
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