Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
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Freescale Semiconductor
1.3.18
On-Chip Voltage Regulator (VREG)
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Linear voltage regulator with bandgap reference
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Low-voltage detect (LVD) with low-voltage interrupt (LVI)
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Power-on reset (POR) circuit
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Low-voltage reset (LVR)
1.3.19
Background Debug (BDM)
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Background debug module (BDM) with single-wire interface
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Non-intrusive memory access commands
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Supports in-circuit programming of on-chip nonvolatile memory
1.3.20
Debugger (DBG)
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Three comparators A, B, C, and D to monitor CPU buses
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Trace buffer with depth of 64 entries
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Comparator A and C compares full address bus and 16-bit data bus with mask register
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Three modes: simple address/data match, inside address range, or outside address range
1.3.21
SSD
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Programmable Full Step State
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Programmable Integration polarity
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Blanking (recirculation) state
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16-bit Integration Accumulator register
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16-Bit Modulus Down Counter with interrupt
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Multiplex two stepper motors
1.3.22
INT (interrupt module)
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Seven levels of nested interrupts
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Flexible assignment of interrupt sources to each interrupt level.
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External non-maskable high priority interrupt (XIRQ)
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The following inputs can act as Wake-up Interrupts
— IRQ and non-maskable XIRQ
— CAN receive pins
— SCI receive pins
— Depending on the package option up to 25 pins on ports R, S, T and AD, configurable as rising
or falling edge sensitive
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