S12X Debug (S12XDBGV3) Module
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
225
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored.
•
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin, End, and Mid alignment of tracing to trigger
6.1.4
Modes of Operation
The S12XDBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.
Thus breakpoints, comparators, and CPU12X bus tracing are disabled . When the CPU12X enters active
BDM Mode through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG
remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
Table 6-3. Mode Dependent Restriction Summary
BDM
Enable
BDM
Active
MCU
Secure
Comparator
Matches Enabled
Breakpoints
Possible
Tagging
Possible
Tracing
Possible
x
x
1
Yes
Yes
Yes
No
0
0
0
Yes
Only SWI
Yes
Yes
0
1
0
Active BDM not possible when not enabled
1
0
0
Yes
Yes
Yes
Yes
1
1
0
No
No
No
No
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