S12X Debug (S12XDBGV3) Module
MC9S12XHY-Family Reference Manual, Rev. 1.01
236
Freescale Semiconductor
The trigger priorities described in
Table 6-39
dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
6.3.2.7.3
Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in
Figure 6-1
and described in
Section 6.3.2.8.1”
. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
0101
Match3 triggers to Final State....... Other matches have no effect
0110
Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
0111
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
1000
Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
1001
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
1010
Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
1011
Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect
1100
Match2 triggers to State1..... Match3 trigger to Final State
1101
Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State
1110
Reserved. (No match triggers state sequencer transition)
1111
Reserved. (No match triggers state sequencer transition)
Address: 0x0027
7
6
5
4
3
2
1
0
R
0
0
0
0
SC3
SC2
SC1
SC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-11. Debug State Control Register 3 (DBGSCR3)
Table 6-23. DBGSCR3 Field Descriptions
Field
Description
3–0
SC[3:0]
These bits select the targeted next state whilst in State3, based upon the match event.
Table 6-24. State3 — Sequencer Next State Selection
SC[3:0]
Description
0000
Any match triggers to state1
0001
Any match triggers to state2
Table 6-22. State2 —Sequencer Next State Selection (continued)
SC[3:0]
Description
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