S12X Debug (S12XDBGV3) Module
MC9S12XHY-Family Reference Manual, Rev. 1.01
238
Freescale Semiconductor
Comparators B and D consist of four register bytes (three address bus compare registers and a control
register).
Each set of comparator registers is accessible in the same 8-byte window of the register address map and
can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed
through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with
data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for
comparators B and D differ from those of comparators A and C.
6.3.2.8.1
Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Read: Anytime. See
Table 6-26
for visible register encoding.
Write: If DBG not armed. See
Table 6-26
for visible register encoding.
WARNING
DBGXCTL[1] is reserved. Setting this bit maps the corresponding comparator to an
Table 6-25. Comparator Register Layout
0x0028
CONTROL
Read/Write
Comparators A,B,C,D
0x0029
ADDRESS HIGH
Read/Write
Comparators A,B,C,D
0x002A
ADDRESS MEDIUM
Read/Write
Comparators A,B,C,D
0x002B
ADDRESS LOW
Read/Write
Comparators A,B,C,D
0x002C
DATA HIGH COMPARATOR
Read/Write
Comparator A and C only
0x002D
DATA LOW COMPARATOR
Read/Write
Comparator A and C only
0x002E
DATA HIGH MASK
Read/Write
Comparator A and C only
0x002F
DATA LOW MASK
Read/Write
Comparator A and C only
Address: 0x0028
7
6
5
4
3
2
1
0
R
0
NDB
TAG
BRK
RW
RWE
reserved
COMPE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-13. Debug Comparator Control Register (Comparators A and C)
Address: 0x0028
7
6
5
4
3
2
1
0
R
SZE
SZ
TAG
BRK
RW
RWE
reserved
COMPE
W
Reset
0
0
0
0
0
0
0
0
Figure 6-14. Debug Comparator Control Register (Comparators B and D)
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