S12X Debug (S12XDBGV3) Module
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
239
unimplemented bus, thus preventing proper operation.
The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are
visible in the 8-byte window from 0x0028 to 0x002F as shown in
Section Table 6-26.
Table 6-26. Comparator Address Register Visibility
COMRV
Visible Comparator
00
DBGACTL, DBGAAH ,DBGAAM, DBGAAL, DBGADH, DBGADL, DBGADHM, DBGADLM
01
DBGBCTL, DBGBAH, DBGBAM, DBGBAL
10
DBGCCTL, DBGCAH, DBGCAM, DBGCAL, DBGCDH, DBGCDL, DBGCDHM, DBGCDLM
11
DBGDCTL, DBGDAH, DBGDAM, DBGDAL
Table 6-27. DBGXCTL Field Descriptions
Field
Description
7
SZE
(Comparators
B and D)
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
6
NDB
(Comparators
A and C
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. Furthermore data bus bits can be
individually masked using the comparator data mask registers. This bit is only available for comparators A
and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for
comparators B and D.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
6
SZ
(Comparators
B and D)
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
This bit position has NDB functionality for comparators A and C
0 Word access size will be compared
1 Byte access size will be compared
5
TAG
Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the
matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.
0 Trigger immediately on match
1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated
4
BRK
Break — This bit controls whether a channel match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
tracing, if active, is terminated and the module disarmed.
3
RW
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator . The RW bit is not used if RWE = 0.
0 Write cycle will be matched
1 Read cycle will be matched
2
RWE
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator. This bit is not used for tagged operations.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
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