Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
24
Freescale Semiconductor
NOTE
Reserved register space shown in
Table 1-2
is not allocated to any module.
This register space is reserved for future use. Writing to these locations have
no effect. Read access to these locations returns zero.
Figure 1-2
shows MC9S12XHY family CPU and BDM local address translation to the global memory
map. It indicates also the location of the internal resources in the memory map.
Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return undefined data values.
A CPU access to any unimplemented space causes an illegal address reset.
The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block
sizes are listed in
Table 1-3
.
0x0240–0x029F
PIM (port integration module)
96
791
0x02A0–0x02CF
TIM1(timer module)
48
795
0x02D0–0x02EF
Reserved
32
0x02F0–0x02F7
Voltage regulator
8
797
0x02F8–0x02FF
Reserved
8
0x0300–0x03FF
Reserved
256
0x0400–0x07FF
Reserved
1024
Address
Module
Size
(Bytes)
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