S12XE Clocks and Reset Generator (S12XECRGV2)
MC9S12XHY-Family Reference Manual, Rev. 1.01
264
Freescale Semiconductor
7.3.2.2
S12XECRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the IPLL multiplier steps.
Read: Anytime
Write: Anytime except when PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For
correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in
Figure 7-3
. Setting the REFFRQ[1:0] bits wrong can result in a non functional IPLL
(no locking and/or insufficient stability).
7.3.2.3
S12XECRG Post Divider Register (POSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the
final divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 f
PLL
= f
VCO
(divide by one).
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
REFFRQ[1:0]
REFDIV[5:0]
W
Reset
0
0
0
0
0
0
0
0
Figure 7-4. S12XECRG Reference Divider Register (REFDV)
Table 7-3. Reference Clock Frequency Selection
REFCLK Frequency Ranges
REFFRQ[1:0]
1MHz <= f
REF
<= 2MHz
00
2MHz < f
REF
<= 6MHz
01
6MHz < f
REF
<= 12MHz
10
f
REF
>12MHz
11
f
REF
f
OSC
REFDIV
1
+
(
)
------------------------------------
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