S12XE Clocks and Reset Generator (S12XECRGV2)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
265
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
If POSTDIV = $00 then f
PLL
is identical to f
VCO
(divide by one).
7.3.2.4
S12XECRG Flags Register (CRGFLG)
This register provides S12XECRG status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
0
0
0
POSTDIV[4:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-5. S12XECRG Post Divider Register (POSTDIV)
Module Base + 0x0003
7
6
5
4
3
2
1
0
R
RTIF
PORF
LVRF
LOCKIF
LOCK
ILAF
SCMIF
SCM
W
Reset
0
Note 1
Note 2
Note 3
0
0
0
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
= Unimplemented or Reserved
Figure 7-6. S12XECRG Flags Register (CRGFLG)
f
PLL
f
VCO
2xPOSTDIV
(
)
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