S12XE Clocks and Reset Generator (S12XECRGV2)
MC9S12XHY-Family Reference Manual, Rev. 1.01
276
Freescale Semiconductor
7.4
Functional Description
7.4.1
Functional Blocks
7.4.1.1
Phase Locked Loop with Internal Filter (IPLL)
The IPLL is used to run the MCU from a different time base than the incoming OSCCLK.
Figure 7-15
shows a block diagram of the IPLL.
Figure 7-15. IPLL Functional Diagram
For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency
REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the
SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of
2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,...
to 62 to generate the PLLCLK.
.
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1) then f
BUS
= f
PLL
/ 2.
IF POSTDIV = $00 the f
PLL
is identical to f
VCO
(divide by one)
Several examples of IPLL divider settings are shown in
Table 7-14
. Shaded rows indicated that these
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
•
Use lowest possible f
VCO
/ f
REF
ratio (SYNDIV value).
•
Use highest possible REFCLK frequency f
REF
.
REDUCED
CONSUMPTION
OSCILLATOR
EXTAL
XTAL
OSCCLK
PLLCLK
REFERENCE
PROGRAMMABLE
DIVIDER
PDET
PHASE
DETECTOR
REFDIV[5:0]
LOOP
PROGRAMMABLE
DIVIDER
SYNDIV[5:0]
VCO
LOCK
UP
DOWN
LOCK
DETECTOR
REFCLK
FBCLK
V
DDPLL
/V
SSPLL
CLOCK
MONITOR
V
DDPLL
/V
SSPLL
V
DD
/V
SS
Supplied by:
CPUMP
AND
FILTER
POST
PROGRAMMABLE
DIVIDER
POSTDIV[4:0]
VCOCLK
f
PLL
2
f
OSC
SYNDIV
1
+
REFDIV
1
+
[
]
2
POSTDIV
×
[
]
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