S12XE Clocks and Reset Generator (S12XECRGV2)
MC9S12XHY-Family Reference Manual, Rev. 1.01
282
Freescale Semiconductor
NOTE
In order to detect a potential clock loss the CME bit should always be
enabled (CME = 1).
If CME bit is disabled and the MCU is configured to run on PLLCLK, a loss
of external clock (OSCCLK) will not be detected and will cause the system
clock to drift towards lower frequencies. As soon as the external clock is
available again the system clock ramps up to its IPLL target frequency. If
the MCU is running on external clock any loss of clock will cause the
system to go static.
7.4.3
Low Power Options
This section summarizes the low power options available in the S12XECRG.
7.4.3.1
Run Mode
This is the default mode after reset.
The RTI can be stopped by setting the associated rate select bits to zero.
The COP can be stopped by setting the associated rate select bits to zero.
7.4.3.2
Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of
the individual bits in the CLKSEL register. All individual Wait Mode configuration bits can be superposed.
This provides enhanced granularity in reducing the level of power consumption during Wait Mode.
Table 7-15
lists the individual configuration bits and the parts of the MCU that are affected in Wait Mode.
After executing the WAI instruction the core requests the S12XECRG to switch MCU into Wait Mode.
The S12XECRG then checks whether the PLLWAI bit is asserted. Depending on the configuration the
S12XECRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables
the IPLL.
There are two ways to restart the MCU from Wait Mode:
1. Any reset
2. Any interrupt
Table 7-15. MCU Configuration During Wait Mode
PLLWAI
RTIWAI
COPWAI
IPLL
Stopped
—
—
RTI
—
Stopped
—
COP
—
—
Stopped
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