Pierce Oscillator (S12XOSCLCPV2)
MC9S12XHY-Family Reference Manual, Rev. 1.01
290
Freescale Semiconductor
8.1.3
Block Diagram
Figure 8-1
shows a block diagram of the XOSC.
Figure 8-1. XOSC Block Diagram
8.2
External Signal Description
This section lists and describes the signals that connect off chip
8.2.1
VDDPLL and VSSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (V
DDPLL
) and ground (V
SSPLL
) for the XOSC circuitry. This
allows the supply voltage to the XOSC to use an independent bypass capacitor.
8.2.2
EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the
internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator
amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived
EXTAL
XTAL
Gain Control
V
DDPLL
= 1.8 V
Rf
OSCCLK
Monitor_Failure
Clock
Monitor
Peak
Detector
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