Voltage Regulator (S12VREGL3V3V1)
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
303
9.3.2
Register Descriptions
This section describes all the VREG_3V3 registers and their individual bits.
9.3.2.1
H
igh
T
emperature
Control Register (VREGHTCL)
The VREGHTCL register allows to configure the VREG temperature sense features.
0x02F0
7
6
5
4
3
2
1
0
R
0
0
VSEL
VAE
HTEN
HTDS
HTIE
HTIF
W
Reset
0
0
0
1
0
0
0
0
= Unimplemented or Reserved
Table 9-4. VREGHTCL Field Descriptions
Field
Description
7, 6
Reserved
These reserved bits are used for test purposes and writable only in special modes.
They must remain clear for correct temperature sensor operation.
5
VSEL
Voltage Access Select Bit — If set, the bandgap reference voltage V
BG
can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). The internal access must be enabled by bit VAE.
See device level specification for connectivity.
0 An internal temperature proportional voltage V
HT
can be accessed internally if VAE is set.
1 Bandgap reference voltage V
BG
can be accessed internally if VAE is set.
4
VAE
Voltage Access Enable Bit — If set, the voltage selected by bit VSEL can be accessed internally (i.e.
multiplexed to an internal Analog to Digital Converter channel). See device level specification for connectivity.
0 Voltage selected by VSEL can not be accessed internally (i.e. External analog input is connected to Analog
to Digital Converter channel).
1 Voltage selected by VSEL can be accessed internally.
3
HTEN
High Temperature Enable Bit — If set the temperature sense is enabled.
0 The temperature sense is disabled.
1 The temperature sense is enabled.
2
HTDS
High Temperature Detect Status Bit —
This read-only status bit reflects the temperature status. Writes have no effect.
0 Temperature T
DIE
is below level T
HTID
or RPM or Shutdown Mode.
1 Temperature T
DIE
is above level T
HTIA
and FPM.
1
HTIE
High Temperature Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever HTIF is set.
0
HTIF
High Temperature Interrupt Flag — HTIF — High Temperature Interrupt Flag
HTIF is set to 1 when HTDS status bit changes. This flag can only be cleared by writing a 1.}Writing a 0 has no
effect. If enabled (HTIE=1), HTIF causes an interrupt request.
0 No change in HTDS bit.
1 HTDS bit has changed.
Note: On entering the reduced power mode the HTIF is not cleared by the VREG.
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