Voltage Regulator (S12VREGL3V3V1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
310
Freescale Semiconductor
9.4
Functional Description
9.4.1
General
Module VREG_3V3 is a voltage regulator, as depicted in
Figure 9-1
. The regulator functional elements
are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on
reset module (POR), and a low-voltage reset module (LVR)and a high temperature sensor (HTD).
9.4.2
Regulator Core (REG)
Respectively its regulator core has three parallel, independent regulation loops (REG1,REG2 and REG3).
REG1 and REG3 differ only in the amount of current that can be delivered.
The regulators are linear regulator with a bandgap reference when operated in Full Performance Mode.
They act as a voltage clamp in Reduced Power Mode. All load currents flow from input VDDR to VSS or
VSSPLL. The reference circuits are supplied by VDDA and VSSA.
9.4.2.1
Full Performance Mode
In Full Performance Mode, the output voltage is compared with a reference voltage by an operational
amplifier. The amplified input voltage difference drives the gate of an output transistor.
9.4.2.2
Reduced Power Mode
In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to
reduce power consumption. Mode switching from reduced power to full performance requires a transition
time of t
vup
, if the voltage regulator is enabled.
9.4.3
Low-Voltage Detect (LVD)
Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input
voltage (V
DDA
–V
SSA
) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever
status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode
or Shutdown Mode.
9.4.4
Power-On Reset (POR)
This functional block monitors VDD. If V
DD
is below V
PORD
, POR is asserted; if V
DD
exceeds V
PORD
,
the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-on
sequence.
9.4.5
Low-Voltage Reset (LVR)
Block LVR monitors the supplies VDD, VDDX and VDDF. If one (or more) drops below it’s
corresponding assertion level, signal LVR asserts; if all VDD,VDDX and VDDF supplies are above their
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