Analog-to-Digital Converter (ADC12B12CV1) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
319
10.2
Signal Description
This section lists all inputs to the ADC12B12C block.
10.2.1
Detailed Signal Descriptions
10.2.1.1
ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
This pin serves as the analog input Channel
x
. It can also be configured as digital port or external trigger
for the ATD conversion.
10.2.1.2
ETRIG3, ETRIG2, ETRIG1, ETRIG0
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connection of these inputs!
10.2.1.3
V
RH
, V
RL
V
RH
is the high reference voltage, V
RL
is the low reference voltage for ATD conversion.
10.2.1.4
V
DDA
, V
SSA
These pins are the power supplies for the analog circuitry of the ADC12B12C block.
10.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC12B12C.
10.3.1
Module Memory Map
Figure 10-2
gives an overview on all ADC12B12C registers.
NOTE
Register Address = Base A Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
ATDCTL0
R
Reserved
0
0
0
WRAP3
WRAP2
WRAP1
WRAP0
W
0x0001
ATDCTL1
R
ETRIGSEL
SRES1
SRES0
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
W
0x0002
ATDCTL2
R
0
AFFC
ICLKSTP ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACMPIE
W
= Unimplemented or Reserved
Figure 10-2. ADC12B12C Register Summary (Sheet 1 of 3)
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