Analog-to-Digital Converter (ADC12B12CV1) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.01
326
Freescale Semiconductor
10.3.2.4
ATD Control Register 3 (ATDCTL3)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x0003
7
6
5
4
3
2
1
0
R
DJM
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
W
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-6. ATD Control Register 3 (ATDCTL3)
Table 10-8. ATDCTL3 Field Descriptions
Field
Description
7
DJM
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 10-9
gives examples ATD results for an input signal range between 0 and 5.12 Volts.
6–3
S8C, S4C,
S2C, S1C
Conversion Sequence Length — These bits control the number of conversions per sequence.
Table 10-10
shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
to HC12 family.
2
FIFO
Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first conversion appears in the first result register
(ATDDR0), the second result in the second result register (ATDDR1), and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
file, the current conversion result will be placed.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the first
result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register
(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion
(ETRIG=1).
Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode
may or may not be useful in a particular application to track valid data.
If this bit is one, automatic compare of result registers is always disabled, that is ADC12B12C will behave as if
ACMPIE and all CPME[n] were zero.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
1–0
FRZ[1:0]
Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in
Table 10-11
. Leakage onto the storage node and comparator reference capacitors
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
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