Analog-to-Digital Converter (ADC12B12CV1) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.01
338
Freescale Semiconductor
10.4
Functional Description
The ADC12B12C is structured into an analog sub-block and a digital sub-block.
10.4.1
Analog Sub-Block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V
DDA
and V
SSA
allow to isolate noise of other MCU circuitry from the analog sub-block.
10.4.1.1
Sample and Hold Machine
The Sample and Hold (S/H) Machine accepts analog signals from the external world and stores them as
capacitor charge on a storage node.
During the sample process the analog input connects directly to the storage node.
The input analog signals are unipolar and must fall within the potential range of V
SSA
to V
DDA
.
During the hold process the analog input is disconnected from the storage node.
10.4.1.2
Analog Input Multiplexer
The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold
machine.
10.4.1.3
Analog-to-Digital (A/D) Machine
The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8
or 10 or 12 bits. The A/D machine uses a successive approximation architecture. It functions by comparing
the stored analog sample potential with a series of digitally generated analog potentials. By following a
binary search algorithm, the A/D machine locates the approximating potential that is nearest to the
sampled potential.
When not converting the A/D machine is automatically powered down.
Only analog input signals within the potential range of V
RL
to V
RH
(A/D reference potentials) will result
in a non-railed digital output code.
10.4.2
Digital Sub-Block
This subsection explains some of the digital features in more detail. See
Section 10.3.2, “Register
Descriptions”
for all details.
10.4.2.1
External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to the external environment
events rather than relying on software to signal the ATD module when ATD conversions are to take place.
The external trigger signal (out of reset ATD channel 11, configurable in ATDCTL1) is programmable to
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