Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XHY-Family Reference Manual, Rev. 1.01
352
Freescale Semiconductor
11.3.2.4
MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
Table 11-7. Baud Rate Prescaler
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Prescaler value (P)
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
:
:
:
:
:
:
:
1
1
1
1
1
1
64
Module Base + 0x0003
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
7
6
5
4
3
2
1
0
R
SAMP
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
W
Reset:
0
0
0
0
0
0
0
0
Figure 11-7. MSCAN Bus Timing Register 1 (CANBTR1)
Table 11-8. CANBTR1 Register Field Descriptions
Field
Description
7
SAMP
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit
(1)
.
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
1. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
6-4
TSEG2[2:0]
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Figure 11-44
). Time segment 2 (TSEG2) values are programmable as shown in
Table 11-9
.
3-0
TSEG1[3:0]
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
of the sample point (see
Figure 11-44
). Time segment 1 (TSEG1) values are programmable as shown in
Table 11-10
.
electronic components distributor
