Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
353
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
Table 11-9
and
Table 11-10
).
Eqn. 11-1
11.3.2.5
MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
Table 11-9. Time Segment 2 Values
TSEG22
TSEG21
TSEG20
Time Segment 2
0
0
0
1 Tq clock cycle
(1)
1. This setting is not valid. Please refer to
Table 11-37
for valid settings.
0
0
1
2 Tq clock cycles
:
:
:
:
1
1
0
7 Tq clock cycles
1
1
1
8 Tq clock cycles
Table 11-10. Time Segment 1 Values
TSEG13
TSEG12
TSEG11
TSEG10
Time segment 1
0
0
0
0
1 Tq clock cycle
(1)
1. This setting is not valid. Please refer to
Table 11-37
for valid settings.
0
0
0
1
2 Tq clock cycles
1
0
0
1
0
3 Tq clock cycles
1
0
0
1
1
4 Tq clock cycles
:
:
:
:
:
1
1
1
0
15 Tq clock cycles
1
1
1
1
16 Tq clock cycles
Module Base + 0x0004
Access: User read/write
(1)
7
6
5
4
3
2
1
0
R
WUPIF
CSCIF
RSTAT1
RSTAT0
TSTAT1
TSTAT0
OVRIF
RXF
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-8. MSCAN Receiver Flag Register (CANRFLG)
Bit Time
Prescaler value
(
)
f
CANCLK
------------------------------------------------------
1
TimeSegment1
TimeSegment2
+
+
(
)
•
=
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