Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XHY-Family Reference Manual, Rev. 1.01
364
Freescale Semiconductor
11.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
Section 11.3.3.1,
“Identifier Registers (IDR0–IDR3)
”) of incoming messages in a bit by bit manner (see
Section 11.4.3,
“Identifier Acceptance Filter
”).
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 to Module Base + 0x0013
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
7
6
5
4
3
2
1
0
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
Reset
0
0
0
0
0
0
0
0
Figure 11-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Table 11-22. CANIDAR0–CANIDAR3 Register Field Descriptions
Field
Description
7-0
AC[7:0]
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Module Base + 0x0018 to Module Base + 0x001B
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
7
6
5
4
3
2
1
0
R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
W
Reset
0
0
0
0
0
0
0
0
Figure 11-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
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