Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XHY-Family Reference Manual Rev. 1.01
Freescale Semiconductor
367
Figure 11-24
shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in
Figure 11-25
.
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation
10
.
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
Table 11-26. Message Buffer Organization
Offset
Address
Register
Access
0x00X0
Identifier Register 0
R/W
0x00X1
Identifier Register 1
R/W
0x00X2
Identifier Register 2
R/W
0x00X3
Identifier Register 3
R/W
0x00X4
Data Segment Register 0
R/W
0x00X5
Data Segment Register 1
R/W
0x00X6
Data Segment Register 2
R/W
0x00X7
Data Segment Register 3
R/W
0x00X8
Data Segment Register 4
R/W
0x00X9
Data Segment Register 5
R/W
0x00XA
Data Segment Register 6
R/W
0x00XB
Data Segment Register 7
R/W
0x00XC
Data Length Register
R/W
0x00XD
Transmit Buffer Priority Register
(1)
1. Not applicable for receive buffers
R/W
0x00XE
Time Stamp Register (High Byte)
R
0x00XF
Time Stamp Register (Low Byte)
R
10. Exception: The transmit buffer priority registers are 0 out of reset.
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