Inter-Integrated Circuit (IICV3) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.01
416
Freescale Semiconductor
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt
type by reading the status register.
IIC Interrupt can be generated on
1. Arbitration lost condition (IBAL bit set)
2. Byte transfer condition (TCF bit set)
3. Address detect condition (IAAS bit set)
The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to
the IBF bit in the interrupt service routine.
12.7
Application Information
12.7.1
IIC Programming Examples
12.7.1.1
Initialization Sequence
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer
serial data, an initialization procedure must be carried out, as follows:
1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL
frequency from system clock.
2. Update the ADTYPE of IBCR2 to define the address length, 7 bits or 10 bits.
3. Update the IIC bus address register (IBAD) to define its slave address. If 10-bit address is applied
IBCR2 should be updated to define the rest bits of address.
4. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system.
5. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive
mode and interrupt enable or not.
6. If supported general call, the GCEN in IBCR2 should be asserted.
12.7.1.2
Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the 'master
transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit
(IBB) must be tested to check whether the serial bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data
written to the data register comprises the slave calling address and the LSB set to indicate the direction of
transfer required from the slave.
The bus free time (i.e., the time between a STOP condition and the following START condition) is built
into the hardware that generates the START cycle. Depending on the relative frequencies of the system
IIC
Interrupt
—
—
—
IBAL, TCF, IAAS
bits in IBSR
register
When either of IBAL, TCF or IAAS bits is set
may cause an interrupt based on arbitration
lost, transfer complete or address detect
conditions
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