Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
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switching during operation. The state of the MODC signal is latched into this bit on the rising edge of
RESET.
1.9.1.1
Normal Single-Chip Mode
This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.
1.9.1.2
Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin.
Table 1-9. Chip Modes
Chip Modes
MODC
Normal single chip
1
Special single chip
0
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