Timer Module (TIM16B8CV2) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.01
532
Freescale Semiconductor
To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0
respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the
OC7M register must also be cleared.
To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in
the OC7M register must also be cleared. The settings for these bits can be seen in
Table 16-10
Table 16-10. The OC7 and OCx event priority
Note: in
Table 16-10
, the IOS7 and IOSx should be set to 1
IOSx is the register TIOS bit x,
OC7Mx is the register OC7M bit x,
TCx is timer Input Capture/Output Compare register,
IOCx is channel x,
OMx/OLx is the register TCTL1/TCTL2,
OC7Dx is the register OC7D bit x.
IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value.
16.3.2.9
Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
OC7M7=0
OC7M7=1
OC7Mx=1
OC7Mx=0
OC7Mx=1
OC7Mx=0
TC7=TCx
TC7>TCx
TC7=TCx
TC7>TCx
TC7=TCx
TC7>TCx
TC7=TCx
TC7>TCx
IOCx=OC7Dx
IOC7=OM7/O
L7
IOCx=OC7Dx
+OMx/OLx
IOC7=OM7/O
L7
IOCx=OMx/OLx
IOC7=OM7/OL7
IOCx=OC7Dx
IOC7=OC7D7
IOCx=OC7Dx
+OMx/OLx
IOC7=OC7D7
IOCx=OMx/OLx
IOC7=OC7D7
Module Base + 0x000A
7
6
5
4
3
2
1
0
R
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
W
Reset
0
0
0
0
0
0
0
0
Figure 16-16. Timer Control Register 3 (TCTL3)
Module Base + 0x000B
7
6
5
4
3
2
1
0
R
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
W
Reset
0
0
0
0
0
0
0
0
Figure 16-17. Timer Control Register 4 (TCTL4)
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