Liquid Crystal Display (LCD40F4BV2) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
559
The voltage levels required for the different operating modes are generated internally based on VLCD.
Changing VLCD alters the differential RMS voltage across the segments in the ON and OFF states,
thereby setting the display contrast.
The backplane waveforms are continuous and repetitive every frame. They are fixed within each operating
mode and are not affected by the data in the LCD RAM.
The frontplane waveforms generated are dependent on the state (ON or OFF) of the LCD segments as
defined in the LCD RAM. The LCD40F4BV2 driver hardware uses the data in the LCD RAM to construct
the frontplane waveform to create a differential RMS voltage necessary to turn the segment ON or OFF.
The LCD duty is decided by the DUTY1 and DUTY0 bits in the LCD control register 0 (LCDCR0). The
number of bias voltage levels is determined by the BIAS bit in LCDCR0.
Table 17-9
summarizes the
multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty).
The backplane pins have their corresponding backplane waveform output BP[3:0] in high impedance state
when in the OFF state as indicated in
Table 17-9
. In the OFF state the corresponding pins BP[3:0]can be
used for other functionality, for example as general purpose I/O ports.
17.4.2
Operation in Wait Mode
The LCD40F4BV2 driver system operation during wait mode is controlled by the LCD stop in wait
(LCDSWAI) bit in the LCD control register 1 (LCDCR1). If LCDSWAI is reset, the LCD40F4BV2 driver
system continues to operate during wait mode. If LCDSWAI is set, the LCD40F4BV2 driver system is
turned off during wait mode. In this case, the LCD waveform generation clocks are stopped and the
LCD40F4BV2 drivers pull down to VSSX those frontplane and backplane pins that were enabled before
entering wait mode. The contents of the LCD RAM and the LCD registers retain the values they had prior
to entering wait mode.
17.4.3
Operation in Stop Mode
All LCD40F4BV2 driver system clocks are stopped, the LCD40F4BV2 driver system pulls down to VSSX
those frontplane and backplane pins that were enabled before entering stop mode. Also, during stop mode,
the contents of the LCD RAM and the LCD registers retain the values they had prior to entering stop mode.
As a result, after exiting from stop mode, the LCD40F4BV2 driver system clocks will run (if LCDEN =
1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode.
Table 17-9. LCD Duty and Bias
Duty
LCDCR0 Register
Backplanes
Bias (BIAS = 0)
Bias (BIAS = 1)
DUTY1
DUTY0
BP3
BP2
BP1
BP0
1/1
1/2
1/3
1/1
1/2
1/3
1/1
1/2
1/3
1/4
0
1
1
0
1
0
1
0
OFF
OFF
OFF
BP3
OFF
OFF
BP2
BP2
OFF
BP1
BP1
BP1
BP0
BP0
BP0
BP0
YES
NA
NA
NA
NA
YES
NA
NA
NA
NA
YES
YES
YES
NA
NA
NA
NA
NA
NA
NA
NA
YES
YES
YES
electronic components distributor
