Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
56
Freescale Semiconductor
1.11.2
Vectors
Table 1-11
lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Section Chapter 4 Interrupt (S12XINTV2)
) provides an interrupt vector base register (IVBR) to
relocate the vectors.
Table 1-11. Interrupt Vector Locations (Sheet 1 of 3)
Vector Address
(1)
Interrupt Source
CCR
Mask
Local Enable
Vector base + $F8
Unimplemented instruction trap
None
None
Vector base+ $F6
SWI
None
None
Vector base+ $F4
XIRQ
X Bit
IRQCR (XIRQEN)
Vector base+ $F2
IRQ
I bit
IRQCR (IRQEN)
Vector base+ $F0
Real time interrupt
I bit
CRGINT (RTIE)
Vector base+ $EE
TIM0 timer channel 0
I bit
TIM0TIE (C0I)
Vector base + $EC
TIM0 timer channel 1
I bit
TIM0TIE (C1I)
Vector base+ $EA
TIM0 timer channel 2
I bit
TIM0TIE (C2I)
Vector base+ $E8
TIM0 timer channel 3
I bit
TIM0TIE (C3I)
Vector base+ $E6
TIM0 timer channel 4
I bit
TIM0TIE (C4I)
Vector base + $E4
TIM0 timer channel 5
I bit
TIM0TIE (C5I)
Vector base+ $E2
TIM0 timer channel 6
I bit
TIM0TIE (C6I)
Vector base+ $E0
TIM0 timer channel 7
I bit
TIM0TIE (C7I)
Vector base+ $DE
TIM0 timer overflow
I bit
TIM0TSRC2 (TOF)
Vector base+ $DC
TIM0 Pulse accumulator A overflow
I bit
TIM0PACTL (PAOVI)
Vector base + $DA
TIM0 Pulse accumulator input edge
I bit
TIM0PACTL (PAI)
Vector base + $D8
SPI
I bit
SPICR1 (SPIE, SPTIE)
Vector base+ $D6
SCI0
I bit
SCI0CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $D4
SCI1
I bit
SCI1CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $D2
ATD
I bit
ATDCTL2 (ASCIE)
Vector base + $D0
Reserved
Vector base + $CE
Port AD
I bit
PIEAD (PIEAD7-PIEAD0)
Vector base + $CC
Port R
I bit
PIER (PIER3-PIER0)
Vector base + $CA
Port S
I bit
PIES (PIES6-PIES5)
Vector base + $C8
Reserved
I bit
Vector base + $C6
CRG PLL lock
I bit
CRGINT(LOCKIE)
Vector base + $C4
CRG self-clock mode
I bit
CRGINT(SCMIE)
Vector base + $C2
Reserved
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