256 KByte Flash Module (S12XFTMR256K1V1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
583
All assigned bits in the FERCNFG register are readable and writable.
18.3.1.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Offset Module Base + 0x0005
7
6
5
4
3
2
1
0
R
0
DFDIE
SFDIE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-9. Flash Error Configuration Register (FERCNFG)
Table 18-12. FERCNFG Field Descriptions
Field
Description
1
DFDIE
Double Bit Fault Detect Interrupt Enable — The DFDIE bit controls interrupt generation when a double bit fault
is detected during a Flash block read operation.
0 DFDIF interrupt disabled
1 An interrupt will be requested whenever the DFDIF flag is set (see
Section 18.3.1.8
)
0
SFDIE
Single Bit Fault Detect Interrupt Enable — The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
Section 18.3.1.8
)
1 An interrupt will be requested whenever the SFDIF flag is set (see
Section 18.3.1.8
)
Offset Module Base + 0x0006
7
6
5
4
3
2
1
0
R
CCIF
0
ACCERR
FPVIOL
MGBUSY
RSVD
MGSTAT[1:0]
W
Reset
1
0
0
0
0
0
0
1
1
Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
Section 18.6
).
0
1
= Unimplemented or Reserved
Figure 18-10. Flash Status Register (FSTAT)
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