Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
59
1.11.3.2
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.11.3.3
I/O Pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.11.3.4
Memory
The RAM arrays are not initialized out of reset.
1.12
COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the COPCTL registerare loaded from the Flash
register FOPT. See
Table 1-12
and
Table 1-13
for coding. The FOPT register is loaded from the Flash
configuration field byte at global address 0x7_FF0E during the reset sequence.
If the MCU is secured the COP time-out rate is always set to the longest period (CR[2:0] = 111) after any
reset into Special Single Chip mode.{mcu_9s12xhy256_cop_resetval.s}
1.13
ATD External Trigger Input Connection
Table 1-12. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
CR[2:0] in
COPCTL Register
000
111
001
110
010
101
011
100
100
011
101
010
110
001
111
000
Table 1-13. Initial WCOP Configuration
NV[3] in
FOPT Register
WCOP in
COPCTL Register
1
0
0
1
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