Device Overview MC9S12XHY-Family
MC9S12XHY-Family Reference Manual, Rev. 1.01
60
Freescale Semiconductor
The ATD module includes external trigger inputs ETRIG[3:0]. The external trigger allows the user to
synchronize ATD conversion to external trigger events.
Table 1-14
shows the connection of the external
trigger inputs.
Consult the ATD section for information about the analog-to-digital converter module. References to
freeze mode are equivalent to active BDM mode.
1.14
ATD Channel[17] Connection
Further to the 12 externally available channels, ATD0 features an extra channel[17] that is connected to
the internal temperature sensor at device level. To access this channel ATD must use the channel encoding
SC:CD:CC:CB:CA = 1:0:0:0:1 in ATDCTL5. For more temperature sensor information, please refer to
1.15.1 Temperature Sensor Configuration
.
1.15
VREG Configuration
The device must be configured with the internal voltage regulator enabled. Operation in conjunction with
an external voltage regulator is not supported.
The API trimming register APITR is loaded from the Flash IFR option field at global address 0x40_00F0
bits[5:0] during the reset sequence. Currently factory programming of this IFR range is not supported.
Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does
not support access abort of reserved VREG register space.
1.15.1
Temperature Sensor Configuration
The VREG high temperature trimming register bits VREGHTTR[3:0] are loaded from the internal Flash
during the reset sequence. To use the high temperature interrupt within the specified limits (T
HTIA
and
T
HTID
) these bits must be loaded with 0x8. Currently factory programming is not supported.
The device temperature can be monitored on ATD0 channel[17]. The internal bandgap reference voltage
can also be mapped to ATD0 analog input channel[17]. The voltage regulator VSEL bit when set, maps
the bandgap and, when clear, maps the temperature sensor to ATD0 channel[17].
Table 1-14. ATD External Trigger Sources
External Trigger
Input
Connectivity
ETRIG0
PP1(PWM channel 1)
(1)
1. When LCD segment output driver is enabled on PP1/PP3, the ATD
external trigger function will be unavailable
ETRIG1
PP3(PWM channel 3)
1
ETRIG2
TIM0 Channel output 2
(2)
2. Independ on the TIM0OCPD3/2 bit setting
ETRIG3
TIM0 Channel output 3
2
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