128 KByte Flash Module (S12XFTMR128K1V1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
627
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
Table 19-3. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
6–0
FDIV[6:0]
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms.
Table 19-4
shows recommended values for FDIV[6:0] based on OSCCLK frequency.
Please refer to
Section 19.3.1, “Flash Command Operations
,
”
for more information.
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